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danluu's profile
Dan Luu
Dan Luu
Dan Luu
@danluu

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Dan Luu

@danluu

https://patreon.com/danluu 

danluu.com
Joined December 2008

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    1. Tavis Ormandy‏Verified account @taviso 8 Dec 2019
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      Replying to @danluu @chort0

      Interesting, so if I test 1000 chips, and they all fail, your saying that it's still safe to make this security sensitive? 🤔

      1 reply 0 retweets 0 likes
    2. Dan Luu‏ @danluu 8 Dec 2019
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      Replying to @taviso @chort0

      Come on, do you want to have a discussion or score points? Seems like you're more interesting in just scoring points?

      2 replies 0 retweets 1 like
    3. Dan Luu‏ @danluu 8 Dec 2019
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      Replying to @danluu @taviso @chort0

      This is a nice soundbite that I guess could sound good to someone who doesn't understand hardware at all but doesn't address anything I said.

      1 reply 0 retweets 0 likes
    4. Tavis Ormandy‏Verified account @taviso 8 Dec 2019
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      Replying to @danluu @chort0

      Then help me understand, I test 10 Transmeta chips, and find all of them start miscalculating branches when some unit is heated with some odd instruction sequence. Should I add Transmeta to the whitelist? I would say no, but it sounds like you're saying, that means nothing.

      1 reply 0 retweets 1 like
    5. Dan Luu‏ @danluu 8 Dec 2019
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      Replying to @taviso @chort0

      How many times did you test a set of chips from a vendor and see that outcome? I'm guessing zero? The broader point is that testing with no model of the underlying process is going to lead to testing things that aren't informative at all.

      1 reply 0 retweets 1 like
    6. Dan Luu‏ @danluu 8 Dec 2019
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      Replying to @danluu @taviso @chort0

      For a conventional branch predictor on a semi-modern (P6+ era) out of order processor, it would be pretty surprising to have the critical path run through the branch predictor. Ofc. a metal fix for could change this as could an unconventional design, as well as other things.

      1 reply 0 retweets 0 likes
    7. Dan Luu‏ @danluu 8 Dec 2019
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      Replying to @danluu @taviso @chort0

      Maybe you get "lucky" with some chip and there's some extreme manufacturing variation that causes this failure mode, maybe the wafer was bad in some particular way, etc.

      1 reply 0 retweets 0 likes
    8. Dan Luu‏ @danluu 8 Dec 2019
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      Replying to @danluu @taviso @chort0

      testing a set of chips from one uarch form one vendor and having it pass some particular overclocked test (where passing means not corrupting the EIP while not crashing?) tells you as much about another uarch from the same vendor as it does about a chip from another vendor.

      1 reply 0 retweets 0 likes
    9. Dan Luu‏ @danluu 8 Dec 2019
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      Replying to @danluu @taviso @chort0

      It doesn't even tell you much about another stepping from the same chip (and vendors will sometimes release revisions without updating the stepping since OEMs complain when you officially change the stepping).

      1 reply 0 retweets 0 likes
    10. Dan Luu‏ @danluu 8 Dec 2019
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      Replying to @danluu @taviso @chort0

      Ok, so now you've tested maybe 10 chips from 10 different models of Intel chips and none fail in this way, well that's the expected outcome, what does that tell you about another model from Intel? Same thing it tells you about a Transmeta chip you didn't test.

      1 reply 0 retweets 2 likes
      Dan Luu‏ @danluu 8 Dec 2019
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      Replying to @danluu @taviso @chort0

      Some a priori knowledge you have is that Intel has * high complexity in their chips compared to every non-white listed vendor * cut back on verification effort in the past decade So even after all that testing, you should still expect a greater chance of funny failures on Intel.

      4:31 PM - 8 Dec 2019
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      1 reply 0 retweets 1 like
        1. New conversation
        2. Dan Luu‏ @danluu 8 Dec 2019
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          Replying to @danluu @taviso @chort0

          Someone who's following along on this discussion pointed out https://www.intel.com/content/www/us/en/support/articles/000055650/processors.html …, this isn't the only time Intel has had a bug like this. You couldn't even get a bug like this on a Centaur chip, the logic isn't sophisticated enough.

          1 reply 0 retweets 3 likes
        3. Dan Luu‏ @danluu 8 Dec 2019
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          Replying to @danluu @taviso @chort0

          So after testing 1k chips from Intel, what do you know? If you have some knowledge of CPU internals and talk to Intel verification folks, your prior (IMO) should still be that they're the most likely to have this kind of issue.

          1 reply 0 retweets 0 likes
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