What is RISC? https://danluu.com/risc-definition/ … Hint: it's not about the number of instructions.pic.twitter.com/2YLL4tBWkS
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To be fair, RISC is probably one of the worst named concepts in computer science. John Mashey spent a decade correcting people on Usenet and couldn't stem the tide of people who naively thought that the concept was defined by the name.
People say dynamic programming is a ridiculous name, and it is, but at least it's merely meaningless.pic.twitter.com/vqz7qRD74N
(Assembly, CPU noob) What is RISC about?
See the tweet before the tweet you're replying to :-)https://twitter.com/danluu/status/905827197713342465 …
This one is especially funny because ARMv8 A64 is _way_ closer overall to the classic RISC philosophy than what's been happening in the 32-bit ARM space for a long time.
You never have lived the hype of the acorn archimedes in the 90's and the disappointment for 30 years to feel like RISC was an overpromising product that was underdelivering. Every time it was: RISC is the best, BUT there was %{random} excuse. https://en.wikipedia.org/wiki/Acorn_Archimedes …
RISC-V already starts with mixed instruction sizes and unaligned access in just its base set.
Sorry, so what is the correction of the faulty assumption? Is it that RISC is simply a smaller set of instructions and doesn't put limits on how complex any given instruction can be? Or something else?
Another example of “fat RISC” is Power ISA. It has over 2k instructions, many of them with very complicated semantics. VLE too.
Only person who hasn't tried to parse intel opcodes can say arm is NOT RISC.
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