Dan Luu

AFAIK some of the more complex ARM cores use uOPs however the decode pipeline is far less complicated (I don’t know the ins and outs of arm though so better double check me)

Do instruction caches cover uOPs or incoming bytestreams, sizewise?

I couldn’t say with certainty, best to ask an expert

Heh @danluu — thoughts? Curious about “intrinsic” x86 vs arm advantages given 2019 CPU microarchitecture trends.

I only seriously studied this for ARMv7, haven't really looked into ARMv8, but I'd expect this to be a relatively small impact relative to other factors, at least for "high performance" chips (including chips used in high-end cell phones as "high performance".

When we implemented an ARMv7 decoder, it was larger than our x86 decoder. This is a little unfair, since the decoder would've been smaller if our backend had originally been designed for ARM, but ARMv7 has a bunch of gross stuff that's not trivial to handle regardless of backend.

I believe a lot of that stuff is gone in ARMv8, but people don't really talk about the ARMv7 penalty the way people talk about the x86 penalty even though I think these two things aren't really so different, so I think it's mostly cultural that people say this about x86.

I'm not saying you can't do better than x86. You can do better. But if I were trying to make a low power chip with at-least iPhone performance, x86 or not would be the low order bit behind having a good micro-arch, making sure we have good circuit designers, etc.