Wow, this is such a cool idea. Translating regular instructions to SIMD instructions in order to run 16 copies of the same program at once, for fuzzing!https://gamozolabs.github.io/fuzzing/2018/10/14/vectorized_emulation.html …
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Replying to @comex @RichFelker
Yeah, AVX-512 is really powerful. I wonder if the endgame of AVX-512 is using it for their GPU ISA, Larrabee-style.
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Is the x86 pipeline really suitable for GPU workloads?
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I’m not sure that they’ll literally share the same *cores* anytime soon. But sharing the same ISA (at least in part) seems reasonable to me. What I was imagining was CPU-like “big” x86 cores and GPU-like “little” x86 cores on the same die sharing a single SIMD ISA.
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Isn’t that pretty much exactly Larrabee though? Larrabee was a separate chip rather than on-die, and its 512-bit instructions were slightly different from AVX-512, but other than that it’s the same idea. I guess a new attempt could be less minimalist wrt graphics-specific HW.
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…and admittedly, http://tomforsyth1000.github.io/blog.wiki.html#%5B%5BWhy%20didn%27t%20Larrabee%20fail%3F%5D%5D … says Larrabee failed at graphics “mainly for reasons of time and politics”, so perhaps a new attempt could succeed. Oh, and modern GPUs do more compute, so Larrabee’s relative strength at compute would be better suited to today’s games.
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Still, I feel like Intel would want to stay far away from anything that looks like just a repeat of Larrabee.
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