(Also, the ‘soft MMU’ thing makes me wonder how expensive it would be for Intel or others to support *optional* byte-wise access permissions in their CPUs. It would allow for so many cool hacks for emulators of all kinds, as well as debuggers…)
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Yeah, AVX-512 is really powerful. I wonder if the endgame of AVX-512 is using it for their GPU ISA, Larrabee-style.
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Is the x86 pipeline really suitable for GPU workloads?
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I’m not sure that they’ll literally share the same *cores* anytime soon. But sharing the same ISA (at least in part) seems reasonable to me. What I was imagining was CPU-like “big” x86 cores and GPU-like “little” x86 cores on the same die sharing a single SIMD ISA.
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Isn’t that pretty much exactly Larrabee though? Larrabee was a separate chip rather than on-die, and its 512-bit instructions were slightly different from AVX-512, but other than that it’s the same idea. I guess a new attempt could be less minimalist wrt graphics-specific HW.
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…and admittedly, http://tomforsyth1000.github.io/blog.wiki.html#%5B%5BWhy%20didn%27t%20Larrabee%20fail%3F%5D%5D … says Larrabee failed at graphics “mainly for reasons of time and politics”, so perhaps a new attempt could succeed. Oh, and modern GPUs do more compute, so Larrabee’s relative strength at compute would be better suited to today’s games.
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Still, I feel like Intel would want to stay far away from anything that looks like just a repeat of Larrabee.
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Thanks for the kind words! Let me know if there is anything you would like to hear more about. I'm getting some great feedback on what people are looking for. The SoftMMU seems to be what people are most interested in. It also applies to QEMU as well which makes it portable
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This is pretty much what languages like ISPC do with scalar kernels. Unstructured flow control gets pretty hairy, and divergent addresses mean you're going to thrash the caches. But it's certainly interesting to try out.
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It reminds me of the great TMC computers.
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Wow. There is EPT sub-pages which supports 64 byte granularity iirc. I have been working on something vaguely similar but not quite as wow: https://rv8.io (also I am one of the RISC-V port maintainers for QEMU). I’m interested in doing a Hard MMU port of RISC-V on x86.
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Wait, you can still by Xeon Phis? I thought they were (sadly) discontinued.
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You can buy a Skylake-X (i9-9980XE) or Cannonlake-U (i3-8121U), both of which have the latest generation of AVX-512. I would like to map the RISC-V vector extension to AVX-512 in binary translation. Variable length Vector on Packed SIMD. An ISA simplification layer essentially.
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Or...u could use a quantum computer to find a load of exploits and bugs by fuzzing in just a few seconds!
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