@cmuratori 2mb pages would drastically increase the amount of memory you could touch at a time before having a TLB miss, etc...
-
-
-
@cmuratori does it compensate for the less number of entries and the incresed cycles penalty?? http://www.7-cpu.com/cpu/IvyBridge.html … - Show replies
New conversation -
-
-
@paniq@anders_breakin@mmalex You must have been a big PS3 fan :)Thanks. Twitter will use this to make your timeline better. UndoUndo
-
-
-
@paniq@anders_breakin@mmalex@cmuratori Hardware should be designed to serve software. Even Itanium had cache rather than scratchpad. -
@paniq@anders_breakin@mmalex@cmuratori And I mention Itanium since it's the ultimate example of "fuck real software" in hardware design.
End of conversation
New conversation -
-
-
@paniq@cmuratori@anders_breakin@mmalex Marketing schmarketing. It was an idiotic idea, and it totally deserved what it got. -
@tom_forsyth@paniq@anders_breakin@mmalex Forsyth laying down some chip-smack... - Show replies
New conversation -
-
-
@paniq@pervognsen@anders_breakin@mmalex@cmuratori CPUs w/o cache are a nightmare. Good for 20 lines of hand tuned asm loops onlyThanks. Twitter will use this to make your timeline better. UndoUndo
-
-
-
@paniq@pervognsen@anders_breakin@mmalex@cmuratori he was talking about multiprocessor coherency -
@kenpex@paniq@anders_breakin@mmalex@cmuratori Yes. Also, caches offer control: prefetch, non-temporals, LRB-style cache line locking.
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.