@rygorous @tom_forsyth @cmuratori for example, suppose every instruction length divides evenly into the largest length! that's okay, I swear
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Replying to @FioraAeterna
@FioraAeterna@tom_forsyth@cmuratori Noo that means RISC-V is out! Can't do that! They have RISC in the name! Officially!1 reply 0 retweets 1 like -
Replying to @rygorous
@rygorous@tom_forsyth@cmuratori omg, wikipedia says GCN and the nvidia ISAs are "RISC", despite having *texture fetch instructions*1 reply 0 retweets 1 like -
Replying to @FioraAeterna
@FioraAeterna@tom_forsyth@cmuratori And GCN has variable-size instrs too. Anyway, RISC has been a worthless label for years.1 reply 0 retweets 1 like -
Replying to @rygorous
@FioraAeterna@tom_forsyth@cmuratori Turns out, many regs and code with lots of simple instrs=good. Everything else, not that important. :)1 reply 0 retweets 0 likes -
Replying to @rygorous
@FioraAeterna@tom_forsyth@cmuratori Everyone can agree that x86s encoding is a mess, but at the same time, if that's killing Intel,1 reply 0 retweets 0 likes -
Replying to @rygorous
@FioraAeterna@tom_forsyth@cmuratori then it sure isn't showing. :)2 replies 0 retweets 0 likes -
Replying to @rygorous
@rygorous@FioraAeterna@tom_forsyth@cmuratori x86 performs good re: code compactness its labyrinthine encoding behaves like a huffman code1 reply 0 retweets 0 likes -
Replying to @orionwl
@orionwl@rygorous@tom_forsyth@cmuratori a very bad, inverted Huffman code3 replies 0 retweets 0 likes -
Replying to @FioraAeterna
@FioraAeterna@rygorous@tom_forsyth@cmuratori RISC archs comparative large code output though,but it may just be better compilers forIntel2 replies 0 retweets 0 likes
@orionwl @FioraAeterna @rygorous @tom_forsyth Well it also doesn't hurt that up until recently there were hardly any registers on x86.
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Replying to @cmuratori
@orionwl@FioraAeterna@rygorous@tom_forsyth (doesn't hurt in this case referring to the size of the instructions).0 replies 0 retweets 1 likeThanks. Twitter will use this to make your timeline better. UndoUndo
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