@FioraAeterna @tom_forsyth @cmuratori And GCN has variable-size instrs too. Anyway, RISC has been a worthless label for years.
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Replying to @rygorous
@FioraAeterna@tom_forsyth@cmuratori Turns out, many regs and code with lots of simple instrs=good. Everything else, not that important. :)1 reply 0 retweets 0 likes -
Replying to @rygorous
@FioraAeterna@tom_forsyth@cmuratori Everyone can agree that x86s encoding is a mess, but at the same time, if that's killing Intel,1 reply 0 retweets 0 likes -
Replying to @rygorous
@FioraAeterna@tom_forsyth@cmuratori then it sure isn't showing. :)2 replies 0 retweets 0 likes -
Replying to @rygorous
@FioraAeterna And the lesson in long-term system design, not just CPUs, is that being a mess is survivable but being dogmatic isn't.2 replies 3 retweets 10 likes -
Replying to @rygorous
@rygorous@FioraAeterna I might suggest the term "intricate puzzle" instead of "mess", although both are appropriate.1 reply 0 retweets 1 like -
Replying to @cmuratori
@rygorous@FioraAeterna When I read the instruction encoding sections in the Intel architecture manual, it read a lot like bomb defusion.1 reply 0 retweets 4 likes -
Replying to @cmuratori
@rygorous@FioraAeterna "If the red wire crosses over the blue wire before the plug for the green wire, you can cut the orange wire if..."2 replies 0 retweets 5 likes -
Replying to @cmuratori
@cmuratori@rygorous@FioraAeterna Anyone who is not appalled by x86 instruction encoding has not truly understood it.1 reply 1 retweet 2 likes -
Replying to @tom_forsyth
@tom_forsyth@rygorous@FioraAeterna Well, I implemented it, and I wasn't... appalled... per se... I guess the feeling is more like...1 reply 0 retweets 0 likes
@tom_forsyth @rygorous @FioraAeterna ... "what the fuck was that?"
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Replying to @cmuratori
@cmuratori@tom_forsyth@rygorous@FioraAeterna As someone writing a small JIT these last few days, I can totally relate to that :-\0 replies 0 retweets 0 likesThanks. Twitter will use this to make your timeline better. UndoUndo
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