@cmuratori I thought that was confirmed? IIRC, the ISA is coming, but it's double-pumped through 256-bit ALUs. Which they have two of.
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@tom_forsyth Can you find some confirmation posted somewhere? I really hope this is true! I am super psyched for AVX-512. - Show replies
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@AndrewLauritzen@tom_forsyth@rygorous@cmuratori I used AVX2 opts at my last job but it ran on in-house commodity servers mostly -
@AndrewLauritzen@tom_forsyth@rygorous@cmuratori it was runtime loaded assembly, so it picked whatever opts the CPU supported - Show replies
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@AndrewLauritzen@kenpex@FioraAeterna@rygorous@cmuratori It will be interesting seeing the perf benefits of AVX512 on an OOO machine. -
@AndrewLauritzen@kenpex@FioraAeterna@rygorous@cmuratori The ISA produces a big step up in efficiency, but OOO can hide many evils. - Show replies
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@AndrewLauritzen@kenpex@FioraAeterna@rygorous@cmuratori I know all the nice integer ones vanished, but does it still have float16?Thanks. Twitter will use this to make your timeline better. UndoUndo
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@AndrewLauritzen The whole problem with any Intel ISA extensions is that they only become useful for mainstream when widely available! -
@AndrewLauritzen "I need to make this even faster on the most bleeding-edge machines, screw our min spec" is not how it works. :) - Show replies
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@AndrewLauritzen I like ISPC but it solves the wrong problem on two axes. -
@AndrewLauritzen One, the code for the newer ISAs is great and the code for ~SSE2 level is neglected. Opposite of what you need. - Show replies
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