I really don't feel it is appropriate to use the term "lock free" to refer to an algorithm that requires locked instructions.
@rygorous Well, I'll put it a different way. The IA-32 ref manual at least thought that it would still LOCK#...
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@rygorous ... if the cache line wasn't already held by that processor. Maybe that's just a lie, but I never got to see chip diagrams :) -
@cmuratori This has nothing to do with chip diagrams and everything to do with cache coherency protocols, which are public!
End of conversation
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