@cmuratori Does that confirm it? Knights Landing is a Xeon Phi part... And hey, 32 registers!
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@cmuratori I wonder how much Intel and AMD cooperates on these things.. Or if it's just "whatever catches on, we'll do too"Thanks. Twitter will use this to make your timeline better. UndoUndo
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@AndrewLauritzen@mattpharr I think people still don't grok how nice ISPC is to use, even if the HW doesn't have masking and suchlike. -
@tom_forsyth@AndrewLauritzen@mattpharr ISPC has definitely inspired a lot of the work I'm doing because CPU vector ISAs are such a PITA... - Show replies
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@AndrewLauritzen@mattpharr@tom_forsyth I thought you knew, CPUs are going to drop floating point altogether because GPUs can do it ;)Thanks. Twitter will use this to make your timeline better. UndoUndo
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@AndrewLauritzen@mattpharr@tom_forsyth I am not sure that AVX512 executes as a single uop in the first implementation...might be ucoded -
@TheKanter you mean in big cores? Clearly Phi is natively 512 bit data paths. - Show replies
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@paniq This is vector, two FMAs (counted as 2 FLOPs) on 8-wide vectors (AVX)/cycle.Thanks. Twitter will use this to make your timeline better. UndoUndo
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@AndrewLauritzen@paniq@mattpharr@tom_forsyth ...if you can keep the ALUs fed. The memory BW gap is bigger. :)Thanks. Twitter will use this to make your timeline better. UndoUndo
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