At some point, someone is going to have to explain why - despite nobody ever wanting this in production code ever, for any reason - the default CSR state for divide by zero on most platforms is fault instead of flush.
-
Show this thread
-
-
Replying to @igorst @cmuratori
Control status register. You can control what happens to the fpu when a divide by zero occurs - but the setting is system wide, so libraries can't safely change it.
1 reply 0 retweets 1 like
Replying to @MogPogSquog @igorst
They are typically not system-wide anymore, they are usually saved and restored with each thread. So it is only libraries that have problems; the primary application programmer can themselves control the CSRs just fine by setting them however they want on each thread.
12:59 AM - 28 Sep 2021
0 replies
0 retweets
2 likes
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.