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cmuratori's profile
Casey Muratori
Casey Muratori
Casey Muratori
@cmuratori

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Casey Muratori

@cmuratori

I'm worried that the baby thinks people can't change.

Seattle
caseymuratori.com
Joined March 2009

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    1. Casey Muratori‏ @cmuratori Jul 30

      It is super weird to me that PHMINPOSUW only exists in 128-bit regs. Since AVX/AVX2 pretend 256-bit regs are 2 128-bit regs, I would have assumed that all 128-bit ops would be in there for 256-bit registers as just two copies of the 128-bit op, but I guess not??

      2 replies 1 retweet 15 likes
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    2. Casey Muratori‏ @cmuratori Jul 30

      Another way to say it would be I would have expected a 256-bit VPHMINPOSUW that generates two "mins", one for each 128-bit half of the input. But instead, there is no 256-bit version at all, even though the 128-bit one still exists _and is very fast_ (not deprecated/microcoded).

      1 reply 0 retweets 7 likes
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      Casey Muratori‏ @cmuratori Jul 30

      So what actually happens in silicon here? Did they actually remove the minpos logic from just the high 128-bit lane of the 256-bit ALU, I guess? Or is that not how these things actually work in practice anymore, and it's actually something completely different?

      7:19 PM - 30 Jul 2021
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      • Rytis Mehmet Cemil Özkaya Zerker Ivan Braidi Sean🐀 Elias Nijs tenuki Tom LePage
      1 reply 0 retweets 10 likes
        1. Raffaele Fragapane‏ @ThE_JacO Jul 31
          Replying to @cmuratori

          From a digital design or mask layout POV could be any number of reasons. Maybe min of 16 16b words breaks timing, fanning to logic couldn't fit, logic changes or optimizations couldn't be fit and a simple doubling (2x16 16b) would break cost because muxes. Only Intel would know

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