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cmuratori's profile
Casey Muratori
Casey Muratori
Casey Muratori
@cmuratori

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Casey Muratori

@cmuratori

I'm worried that the baby thinks people can't change.

Seattle
caseymuratori.com
Joined March 2009

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    1. Geoff Langdale‏ @geofflangdale May 21
      Replying to @geofflangdale @cmuratori @HaroldAptroot

      the upcoming Neoverse cores.

      1 reply 0 retweets 0 likes
    2. Nigel Stephens‏ @arm_nigels May 21
      Replying to @geofflangdale @cmuratori @HaroldAptroot

      Yeah, but at least one is a strict superset of the other!

      1 reply 0 retweets 0 likes
    3. Geoff Langdale‏ @geofflangdale May 21
      Replying to @arm_nigels @cmuratori @HaroldAptroot

      I'm not crazy about Intel's weird side extensions for Cooper Lake for that reason. Still, aside from a couple small corners, the dig on Intel for having weird overlapping ISAs in AVX-512 mostly relies on cancelled products (Cannonlake and Knights*). The thing I find ...

      1 reply 0 retweets 0 likes
    4. Geoff Langdale‏ @geofflangdale May 21
      Replying to @geofflangdale @arm_nigels and

      more frustrating about AVX-512 (relative to what I've seen of SVE/SVE2, and certainly my experiences of NEON) is the lack of orthogonality - especially irritating if you do a lot of working with bytes, as that tends to be the data size that gets the least respect.

      1 reply 0 retweets 0 likes
    5. Nigel Stephens‏ @arm_nigels May 21
      Replying to @geofflangdale @cmuratori @HaroldAptroot

      Sure, I can only really speak for SVE/SVE2. I know that support for 8 and 16-bit was added relatively late to AVX, is that the case for RV too?

      1 reply 0 retweets 0 likes
    6. Geoff Langdale‏ @geofflangdale May 21
      Replying to @arm_nigels @cmuratori @HaroldAptroot

      AVX512 is a collision of 2 different Intel sources of prejudice against small sizes - doing floats first (as per what we could now describe as SSE1 and AVX1) and the 32/64b-centered elements of Knights*, which didn't have small sizes at all. Lots of ops fade out as you ...

      1 reply 0 retweets 1 like
    7. Geoff Langdale‏ @geofflangdale May 21
      Replying to @geofflangdale @arm_nigels and

      get smaller - you can't do masking with logic ops on 8/16 and you can't shift or rotate bytes (except by fixed-ish amounts using GFNI, which is fun). I found NEON a pleasure to work with because you wouldn't have those "wtf" moments wondering why some insn didn't exist.

      1 reply 0 retweets 1 like
    8. Geoff Langdale‏ @geofflangdale May 21
      Replying to @geofflangdale @arm_nigels and

      Not sure about RISC-V as I'm prone to ignore any system that does wild end-zone dances about how elegant their variable width vectors are without shipping *anything*. At least you guys had Fujitsu, and I remember their throughput/latency numbers were decent. :-)

      1 reply 0 retweets 0 likes
    9. Nigel Stephens‏ @arm_nigels May 21
      Replying to @geofflangdale @cmuratori @HaroldAptroot

      Let’s hope we can continue to live up to that 😬

      1 reply 0 retweets 0 likes
    10. Geoff Langdale‏ @geofflangdale May 21
      Replying to @arm_nigels @cmuratori @HaroldAptroot

      I bet you guys know already, but can't tell.😄 Actually, throughput/latency numbers for V1/N2 sooner rather than later would be great. To me this is more significant than the (laudable) simulator/software support. A lot of stuff I've designed lives and dies by these numbers.

      2 replies 0 retweets 0 likes
      Casey Muratori‏ @cmuratori May 21
      Replying to @geofflangdale @arm_nigels @HaroldAptroot

      For what it's worth, when I looked into it more, I felt like the fact that you could get the count directly and use it as the loop increment alleviates some of my fears. So I am less skeptical of the V extension now than I was, although I still have concerns.

      11:05 PM - 21 May 2021
      1 reply 0 retweets 0 likes
        1. New conversation
        2. Geoff Langdale‏ @geofflangdale May 21
          Replying to @cmuratori @arm_nigels @HaroldAptroot

          I'm still skeptical for a couple reasons. I need to see performance numbers. There's an alarming tendency to regard SIMD as a 'scientific computing throughput game' where a few extra cycles of latency are NBD because we're all doing massive matrix multiplies. ...

          1 reply 0 retweets 0 likes
        3. Geoff Langdale‏ @geofflangdale May 21
          Replying to @geofflangdale @cmuratori and

          My taxonomy of SIMD is: 1) traditional SIMD where you're doing one thing over and over, 2) SIMD where the size of the thing you're operating on is big but not unbounded (i.e. "simulate a 256 state NFA") and 3) Uses of SIMD to get at weird functionality not on GPRs (e.g. PSHUFB).

          1 reply 0 retweets 0 likes
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