So does doing final compilation at runtime.
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Sure but one off, if your running at 6 hour simulation that fact that it takes 10 seconds longer to start is not a big factor if that makes it run 2% faster.
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Or it makes it run 2% slower, because there's a CRC mismatch and it runs the wrong code path (AMD), or its a different version of the driver that you optimized for and they broke something (everybody), etc., etc. Stable ISAs have their own significant perf advantages.
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But that requires hardware vendors to either creat bloated instruction sets or add a instruction set decoder like modern cpus that converts it into the hardware specific instructions. Both of these have a high transistor cost increasing core size a lot
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Honestly, that sounds like something you just made up. Taking ARM as an example, since that is a long-lifetime RISC-like ISA which is what a GPU would be worst case, can you show me a modern high-FLOP chip die shot where the _decoder_ is taking a significant portion of the chip?
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Modern ARM cpus do not run ARM internals they translate it into micro ops.
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So, before we continue this discussion, do you actually know what you're talking about, or not? Like do you know what a front-end decoder is or not? Not trying to be insulting, just asking. Because your last tweet makes no sense at all, and I'd like to know why.
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Yes I do. The key difference between GPU ISAs and most modern CPU ISAs is that the GPUs do not have an additional internal ISA and thus save on not needing the transistors to covert into that internal representation
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You didn't answer my question. I asked you to show me some evidence that the decoder on ARM takes up significant die space. You said, "Modern ARM cpus do not run ARM internals they translate it into micro ops." That is a nonsense answer. Do you know why, or not?
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Compared to not having a decoder, are you saying these things do not take up any space?
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OK, so since you refuse to answer my question, this conversation is over.
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