@jqgregory Is there a more detailed explanation somewhere of the "pipeline stall" discussed in this passage from your book? I was asked about it, and I can't think of anything to which it could be referring. (https://imgur.com/76F458o )
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So if somebody has an example of some actual C code someone might write in the real world, where a pre-increment actually compiles to a cycle stall that would disappear if you switch to post-increment, I would like to see it so I can see what they're talking about.
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My best guess is that this was not advice from modern processors - maybe it is based on older processors that had less IPC?
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