I don't know why the accumulator variant has an extra uop but it's always important to remember with x86 that there's a bunch of 1-byte instr variants that only work with the accumulator and look similar in a disasm listing but are completely separate opcodes
Anecdotally, I remember a lot of off-hand comments from Intel people back in the day along the lines of "nobody wants to touch the decoder".
-
-
FWIW the same seems to be true for ARM, and yet most current 64-bit ARMs have 3 of them for the 3 encodings they support. (A32, T32, A64)
-
a separate thing is that in the P54C cores specifically, really _nobody_ wants to touch the decoders, but that's for other reasons.
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.