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cmuratori's profile
Casey Muratori
Casey Muratori
Casey Muratori
@cmuratori

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Casey Muratori

@cmuratori

I'm worried that the baby thinks people can't change.

Seattle
caseymuratori.com
Joined March 2009

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    1. Fabian Giesen‏ @rygorous 29 Apr 2019
      Replying to @rygorous @Jonathan_Blow @cmuratori

      I don't know why the accumulator variant has an extra uop but it's always important to remember with x86 that there's a bunch of 1-byte instr variants that only work with the accumulator and look similar in a disasm listing but are completely separate opcodes

      1 reply 0 retweets 0 likes
    2. Fabian Giesen‏ @rygorous 29 Apr 2019
      Replying to @rygorous @Jonathan_Blow @cmuratori

      I wish AMD64 had thrown out way more of the old 1-byte encodings; all the accumulator ops are super rarely useful, have these weird potholes, and take up really valuable real estate in the opcode map that could've been then used for other things.

      1 reply 0 retweets 3 likes
    3. Fabian Giesen‏ @rygorous 29 Apr 2019
      Replying to @rygorous @Jonathan_Blow @cmuratori

      a whole, connected, 1/16th of the entire 1-byte opcode map (bit pattern 00***10*) is devoted to these things and they're most definitely not worth it

      1 reply 0 retweets 2 likes
    4. Fabian Giesen‏ @rygorous 29 Apr 2019
      Replying to @rygorous @Jonathan_Blow @cmuratori

      Imagine if they'd used that space for, say (random example, didn't look at real-world code to eval how good that particular proposal is) a "src1" prefix that lets you specify a 4-bit register number for the first source (independent of destination) on any GPR instruction

      1 reply 0 retweets 0 likes
    5. Fabian Giesen‏ @rygorous 29 Apr 2019
      Replying to @rygorous @Jonathan_Blow @cmuratori

      That would replace a sizable fraction of all reg-reg moves in x64 code (generally either 2B or 3B) with a 1B prefix, which would be much more generally useful than shorter accumulator ops.

      1 reply 0 retweets 1 like
    6. Fabian Giesen‏ @rygorous 29 Apr 2019
      Replying to @rygorous @Jonathan_Blow @cmuratori

      That particular example is literally just the first thing that came to mind; my point is just that having that amount (and quality) of space freed up is enough for substantial re-engineering, so it's a shame that AMD64 didn't do it. :/

      1 reply 0 retweets 1 like
    7. Fabian Giesen‏ @rygorous 29 Apr 2019
      Replying to @rygorous @Jonathan_Blow @cmuratori

      (It was the one legitimate chance to remove anything from future x86 that anyone ever got.)

      1 reply 0 retweets 2 likes
    8. Casey Muratori‏ @cmuratori 29 Apr 2019
      Replying to @rygorous @Jonathan_Blow

      One assumes it would have been best to take the x86/SSE instruction set and "rebalance the huffman tree" such that you tried to have the size of each encoding correspond to its frequency? But I assume they didn't do this because they still wanted to run x86 at speed...

      1 reply 0 retweets 0 likes
    9. Fabian Giesen‏ @rygorous 29 Apr 2019
      Replying to @cmuratori @Jonathan_Blow

      They wanted to not have a separate decoder, basically, and x86_64 is definitely close enough to do 32b and 64b with the same decoder block (and many internal flag bits).

      2 replies 0 retweets 1 like
    10. Fabian Giesen‏ @rygorous 29 Apr 2019
      Replying to @rygorous @cmuratori @Jonathan_Blow

      it makes perfect sense in that _especially_ before uop caches (which this was) the decoders are a supers-tweaky speed-critical path that nobody wants to make big changes to (or have two of), but we'd be better off now had they done it.

      2 replies 0 retweets 1 like
      Casey Muratori‏ @cmuratori 29 Apr 2019
      Replying to @rygorous @Jonathan_Blow

      Anecdotally, I remember a lot of off-hand comments from Intel people back in the day along the lines of "nobody wants to touch the decoder".

      6:18 PM - 29 Apr 2019
      1 reply 0 retweets 0 likes
        1. New conversation
        2. Fabian Giesen‏ @rygorous 29 Apr 2019
          Replying to @cmuratori @Jonathan_Blow

          FWIW the same seems to be true for ARM, and yet most current 64-bit ARMs have 3 of them for the 3 encodings they support. (A32, T32, A64)

          1 reply 0 retweets 0 likes
        3. Fabian Giesen‏ @rygorous 29 Apr 2019
          Replying to @rygorous @cmuratori

          a separate thing is that in the P54C cores specifically, really _nobody_ wants to touch the decoders, but that's for other reasons.

          1 reply 0 retweets 0 likes
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