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  1. proslijedio/la je Tweet
    prije 16 sati

    Looking for an alternative to Verilog? Bluespec has open sourced the compiler for BSV/BH!!

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  2. prije 16 sati

    Re. open-source compiler (): Tutorials: Three RISC-V processors, buildable/runnable out-of-the-box: {Piccolo,Flute,Toooba}

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  3. prije 16 sati

    Bluespec, Inc. is delighted to open-source our compiler for the BSV/BH High-level Hardware Design Languages. Enjoy!

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  4. proslijedio/la je Tweet
    4. pro 2019.

    Re. "A Tour of the RISC-V ISA Formal Specification" tutorial at Summit, San Jose, December 12, 2019: if you're attending, kindly spend a few minutes to pre-install some stuff: see "Slides_Installation.pdf" at this GitHub repo:

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  5. proslijedio/la je Tweet
    12. ruj 2019.

    In a major breakthrough, an team has created the world's first 16-bit microprocessor—a tech which may keep alive

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  6. proslijedio/la je Tweet
    10. ruj 2019.

    "Shakti C Class now ready for production". -V processors, designed using HLHDL (High-Level Hardware Design Language).

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  7. proslijedio/la je Tweet
    6. ruj 2019.

    ... and the RISC-V processor itself was designed in Bluespec BSV, iterating rapidly many times to find an architecture that would suit the flow.

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  8. proslijedio/la je Tweet
    30. kol 2019.

    Hi . I am biased for sure, but SUPER proud that this nanotube work was powered by . Congrats Max Shulaker and my dad, Arvind. Get on Twitter you guys!

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  9. 31. kol 2019.

    Article in Nature: "Modern microprocessor built from complementary carbon nanotube transistors". instruction set. Designed using .

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  10. proslijedio/la je Tweet
    11. lip 2019.

    thx team RT : introducing - a new not-for-profit global organization to boost the adoption of open-source processors, currently counting 17 sponsors and partners. PULP has proudly contributed its cores

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  11. proslijedio/la je Tweet

    Highly acclaimed award winner and second woman to win a Turing award, Barbara Liskov will receive an Honorary Doctor of Mathematics degree from this week. Congratulations!

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  12. 9. lip 2019.

    Daniel Nenni says: "DAC is now a RISC-V Conference!"

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  13. 15. velj 2019.

    "RISCV on the Verge of Broad Adoption"

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  14. proslijedio/la je Tweet
    8. svi 2017.
    Odgovor korisniku/ci

    Gotta switch to real compiler/static analysis/type checking tools to decrease the noise

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  15. proslijedio/la je Tweet
    8. svi 2017.

    Observation: regex-base code quality tools, like linters, break down at scale. Too many false positives once you're on 10M+ lines.

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  16. 11. srp 2016.

    public rel V1 "Piccolo" implem . Pre-built sims, full Verilog RTL. Eff. 3-stage RV32IM

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  17. proslijedio/la je Tweet
    9. sij 2015.

    Darius Rad and I () will speak and do posters and demos at the 1st Workshop in Monterey Jan 14-15 ()

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  18. 10. ruj 2014.

    CTO Nikhil speaking at CDN Live 9/16, "FPGA Prototyping Enables Rapid Development of Customizable Processors",

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  19. 5. ruj 2013.

    Bluespec Desktop Emulation Now Supports Xilinx 7 Series FPGAs

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