Project idea: Kintex-7 GTX based logic analyzer. * 8 fast channels @ 10 Gsps * TBD slow channels @ 1.25 Gsps (1/8 rate) * 8 MB sample memory = 8M samples * 8 bits, more w/ RLE compression * Comparator based input stage w/ selectable threshold
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Headless (1U?) system w/ 1000base-T interface to host PC. At full memory depth, 8Mx8 samples (64 Mb) over gig-e gives ~15 WFM/s uncompressed. Less deep captures will give proportionally higher performance.
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50 ohm SMA inputs intended for use with external transmission line probes. May also support 100 ohm differential inputs for direct input of LVDS/CML. Also a 10 MHz refclk input and trigger input/output for synchronizing to an oscilloscope.
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BOM wise, you're looking at a $386 @ qty 1 FPGA, a $113 @ qty 1 QDR-II+, eight $37 @ qty 10 comparators, and a $20 @ qty 1 PLL. So about $815 in silicon plus a 4-6 layer controlled impedance PCB. Might have to drop from 8 channels to 6 so I can steal one input per quad for sync
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But I'm looking into options for using some sort of high speed mux to use a normal input channel for sync so I don't have to lose any. Even six channels is a respectable amount: enough to probe DRAM RAS/CAS/WE#CS#/CLK/DQS and leave your scope analog inputs for looking at DQ.
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