Project idea: Kintex-7 GTX based logic analyzer. * 8 fast channels @ 10 Gsps * TBD slow channels @ 1.25 Gsps (1/8 rate) * 8 MB sample memory = 8M samples * 8 bits, more w/ RLE compression * Comparator based input stage w/ selectable threshold
-
-
But I'm looking into options for using some sort of high speed mux to use a normal input channel for sync so I don't have to lose any. Even six channels is a respectable amount: enough to probe DRAM RAS/CAS/WE#CS#/CLK/DQS and leave your scope analog inputs for looking at DQ.
Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
-
-
-
wait, 8 comparators, do you plan to build a delta sigma per channel, or do you plan to multiplex an 8-bit flash ADC?
-
This is an LA, not a scope (although intended to be combined with one for mixed signal captures) - a low cost f/oss competitor to the LeCroy HDA125.
- Još 8 drugih odgovora
Novi razgovor -
-
-
QDR? SDRAM is rather predictable and fast for linear access.
-
I considered QDR-II+ as well. I'd need two of them plus a bit of compression to get 80 Gbps of bandwidth. Both are possibilities for the final system. My prototype is going to be an I/O module for an existing devkit and just capture to BRAM.
Kraj razgovora
Novi razgovor -
Čini se da učitavanje traje već neko vrijeme.
Twitter je možda preopterećen ili ima kratkotrajnih poteškoća u radu. Pokušajte ponovno ili potražite dodatne informacije u odjeljku Status Twittera.