Headless (1U?) system w/ 1000base-T interface to host PC. At full memory depth, 8Mx8 samples (64 Mb) over gig-e gives ~15 WFM/s uncompressed. Less deep captures will give proportionally higher performance.
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50 ohm SMA inputs intended for use with external transmission line probes. May also support 100 ohm differential inputs for direct input of LVDS/CML. Also a 10 MHz refclk input and trigger input/output for synchronizing to an oscilloscope.
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BOM wise, you're looking at a $386 @ qty 1 FPGA, a $113 @ qty 1 QDR-II+, eight $37 @ qty 10 comparators, and a $20 @ qty 1 PLL. So about $815 in silicon plus a 4-6 layer controlled impedance PCB. Might have to drop from 8 channels to 6 so I can steal one input per quad for sync
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But I'm looking into options for using some sort of high speed mux to use a normal input channel for sync so I don't have to lose any. Even six channels is a respectable amount: enough to probe DRAM RAS/CAS/WE#CS#/CLK/DQS and leave your scope analog inputs for looking at DQ.
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Decoupling the acquisition side (specialized, high speed) from the UX/visualization side (a software problem that can be solved on readily available off the shelf hardware) seems like a good move.
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UI would be done in glscopeclient as that already exists and has a good library of protocol decodes etc. What I want is to make something competitive with http://cdn.teledynelecroy.com/files/pdf/hda125-datasheet.pdf … for a fraction of the price.
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slow version can be Artix based I guess ?
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I was talking about on the same device, using ISERDES for the slow channels and GTX for the fast. But a low-cost Artix based version would definitely be doable without massive RTL changes.
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A slow-only version of this, in a Saleae form factor (maybe bigger, like some of the older JLink's) would be awesome enough for an amateur like me...
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What specs would you hope for? I’m poking around at using fast but cheap microcontrollers as logic analyzers.
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Čini se da učitavanje traje već neko vrijeme.
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