JVS via User IO research time re: #MiSTerFPGA ! This is all ya need right here.pic.twitter.com/bKUQRINnzv
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I understand,but at the end is all a trade off between latency and the available GPIOs you want to expend on the JVS adapter. I see the 7x USER_IO GPIOs too valuable, that’s why I’m suggesting that alternative USB via, you for sure already knew. USB HID is really low latency now.
Also, in context "I see the 7x USER_IO GPIOs too valuable" if you are in a JVS environment, all your input is coming over those 2 pins anyway. The rest of your fancy IO really need not APPLY, unless it has it's own JVS node within to daisy chain.
