Ok... bed time. Next goal. "This demonstration shows how to use HPS DDR3 as an external buffer of the frame buffer IP in an FPGA based video pattern generator." https://www.terasic.com.tw/cgi-bin/page/archive_download.pl?Language=English&No=1046&FID=1c19d1d50e0ee9b21678e881004f6d81 …pic.twitter.com/ij6wiFOb8o
12:28 AM - 21 Feb 2021
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