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andreasdotorg's profile
andreasdotorg
andreasdotorg
andreasdotorg
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andreasdotorg

@andreasdotorg

I'm a hacker, pretty much in the old school sense of the word. But I do know IT security too.

Joined April 2008

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    1. whitequark‏ @whitequark Apr 13

      whitequark Retweeted whitequark

      Glasgow is a 50 MHz 1V8/2V5/3V3/3V6/5V0 bus multitool, think Bus Pirate + Bus Blaster + Logic Sniffer all in one reconfigurable package you have 16 pins. put any of {JTAG,SWD,SPI,I2C,USART,…} on any of them, or even use your own protocol core on the FPGA!https://twitter.com/whitequark/status/985037591568199686 …

      whitequark added,

      whitequark @whitequark
      it's getting together pic.twitter.com/5k1BwGQhuR
      Show this thread
      15 replies 67 retweets 256 likes
      Show this thread
    2. whitequark‏ @whitequark Apr 13

      the 16 pins are split among two fully independent ESD protected I/O banks with a DAC+LDO to set the I/O standard and/or power the target, an ADC to sense the target voltage, an alert function to detect faults, and an intrinsic 100 mA current limit for added safety

      2 replies 0 retweets 12 likes
      Show this thread
    3. whitequark‏ @whitequark Apr 13

      the PC interface has peak throughput of ~360 Mbps (bulk endpoints), so you can sample 16 channels at 22.5 Msps, 8 channels at 45 Msps, 4 channels at 90 Msps, and so on you can also download stuff via JTAG -really fast-; instead of bus turnarounds, just use a custom JTAG core

      1 reply 0 retweets 10 likes
      Show this thread
    4. whitequark‏ @whitequark Apr 13

      the somewhat low sampling rate is compensated (for synchronous interfaces) by the fact that the FPGA is able to sample at a defined phase wrt interface clock; so while normally you would need 200 Msps for a bus running at 50 MHz, with Glasgow mere 50 Msps are enough

      2 replies 0 retweets 7 likes
      Show this thread
    5. whitequark‏ @whitequark Apr 13

      if you want one, once the hardware is proven I'll be selling these at an estimated $70 plus shipping

      7 replies 3 retweets 46 likes
      Show this thread
    6. whitequark‏ @whitequark Apr 13

      in case you're wondering, this is basically a scaled down version of @azonenberg's STARSHIPRAIDER, which does 32 channels at 500 MHz, has a 10 GbE host interface, and costs around $1K in BOM+PCB I didn't set out to do that but it turns out this desing space is juts really narrow

      1 reply 0 retweets 9 likes
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    7. whitequark‏ @whitequark Apr 14

      this project is a collaboration with @awygle, who has given invaluable advice on overall design, made all the symbols and footprints and is upstreaming them in KiCAD (the goal is using 100% upstream libraries)

      1 reply 0 retweets 12 likes
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    8. whitequark‏ @whitequark Apr 14

      I think this is about as far as you can go while using only FOSS toolchains for firmware/gateware; if I ever make a sequel for this board it'll be after @oe1cxw finishes Series 7 bitstream reverse-engineering :)

      1 reply 1 retweet 18 likes
      Show this thread
    9. OSS FPGA tools‏ @ico_TC Apr 14
      Replying to @whitequark @oe1cxw

      The documentation of the Xilinx S7 FPGA bitstream is not what is holding us back. Its the availability of a proper working P&R. VPR in its current state does not cut. We need someone qualified who can work on this full time for several months (currently funding is missing).

      3 replies 1 retweet 4 likes
      andreasdotorg‏ @andreasdotorg Apr 15
      Replying to @ico_TC @whitequark @oe1cxw

      I'm probably incredibly clueless, but isn't this "just" a search problem?

      9:39 AM - 15 Apr 2018
      0 replies 0 retweets 0 likes

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