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andreasdotorg's profile
andreasdotorg
andreasdotorg
andreasdotorg
@andreasdotorg

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andreasdotorg

@andreasdotorg

I'm a hacker, pretty much in the old school sense of the word. But I do know IT security too.

Joined April 2008

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    1. Clifford Wolf‏ @oe1cxw Jan 2

      Creating spec for an iCE40UP5K development board. Please reply with your feedback: Anything important missing from that spec?pic.twitter.com/x4TKdVuKyd

      14 replies 8 retweets 32 likes
    2. andreasdotorg‏ @andreasdotorg Jan 2
      Replying to @oe1cxw

      I might be an outlier, but... DRAM.

      2 replies 0 retweets 2 likes
    3. Clifford Wolf‏ @oe1cxw Jan 2
      Replying to @andreasdotorg

      We have one MBit of SPRAM in the FPGA. The chip has only 39 IO pins, so external RAM isn't really an option.

      1 reply 0 retweets 0 likes
    4. andreasdotorg‏ @andreasdotorg Jan 2
      Replying to @oe1cxw

      Ok, good enough reason.

      1 reply 0 retweets 1 like
    5. Jan Gray‏ @jangray Jan 2
      Replying to @andreasdotorg @oe1cxw

      How about some Cypress 512Mb+64 Mb HyperFlash+RAM? ~15 pins? :-) http://www.cypress.com/file/322936/download … No experience, don't know if shipping yet, etc.

      1 reply 0 retweets 1 like
    6. Jan Gray‏ @jangray Jan 2
      Replying to @jangray @andreasdotorg @oe1cxw

      Oh, I see the 39 IOs are already taken. It would be too much to ask to make the dual PMOD pins dual-use for the RAM. Sorry, nevermind.

      1 reply 0 retweets 1 like
    7. Clifford Wolf‏ @oe1cxw Jan 2
      Replying to @jangray @andreasdotorg

      But could be interesting as a module for the dual PMOD port.

      1 reply 0 retweets 1 like
    8. OSS FPGA tools‏ @ico_TC Jan 3
      Replying to @oe1cxw @jangray @andreasdotorg

      There is the dual PMOD hyperRAM module from @bml_khubbard

      3 replies 0 retweets 4 likes
      andreasdotorg‏ @andreasdotorg Feb 18
      Replying to @ico_TC @bml_khubbard

      Hi Kevin, where can I find said HyperRAM module?

      1:05 PM - 18 Feb 2018
      1 reply 0 retweets 0 likes
        1. New conversation
        2. Kevin Hubbard‏ @bml_khubbard Feb 18
          Replying to @andreasdotorg @ico_TC

          Here is an order link https://oshpark.com/shared_projects/XOydkgcZ …. I don't actually have it working yet, still writing Verilog for it, but project got postponed for my Spartan7 project. Once I have a working Verilog design, I will write about it and provide links with layer images, Gerbers, etc.

          1 reply 0 retweets 0 likes
        3. andreasdotorg‏ @andreasdotorg Feb 18
          Replying to @bml_khubbard @ico_TC

          Excellent, thanks! Will keep an eye on it!

          1 reply 0 retweets 0 likes
        4. Kevin Hubbard‏ @bml_khubbard Feb 18
          Replying to @andreasdotorg @ico_TC

          Here is the final layout. The only component other than the HyperRAM is a 0.1uF 0603 cap. There isn't anything on the backside.pic.twitter.com/YHICCs2uwV

          3 replies 0 retweets 1 like
        5. andreasdotorg‏ @andreasdotorg Feb 19
          Replying to @bml_khubbard @ico_TC

          Am I naughty for wishing there was a HyperFlash on the backside?

          1 reply 0 retweets 1 like
        6. 1 more reply

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