Block diagram for LATENTRED switch fabric (management engine etc not shown). Buffer sizes are tentative and haven't been verified by simulation or anything yet. Comments?pic.twitter.com/GR2GQa968p
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can you add a thingie that lets you see current/minimum/maximum/average queue utilisation/filling?
I could definitely add instrumentation for average queue size (random sampling over time). As well as performance counters for things like packets lost to queue overflow.
The design is coming together slowly. 1G line card PCB is ready for tapeout, management CPU board (INTEGRALSTICK) is sch-complete, MAC/VLAN table is tested in sim, 10G PCS core verified on XCVU+ but needs testing on XC7K still. This is my sketch of the packet datapath itself
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