FPGA development is fun...pic.twitter.com/pinz4KvQ0d
⁂ dysfunctional Verilog programmer ✦ shockingly nice under the circumstances ✦ patreon: https://www.patreon.com/user?u=12717330 ⁂
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FPGA development is fun...pic.twitter.com/pinz4KvQ0d
i found and fixed the two bugs -- one bug was a pipeline desynchronisation (the same data being processed with two different values (bad) of the same parameter when that parameter would change value) and a slightly premature strobe signal from the testbench:pic.twitter.com/6M9p4xoDLz
i'm going to work this week on making this design fully-synthesizable (i need to write verilog to generate the synchronisation/timing signals that the testbench currently generates)!
it's *very small*, even for an ice40 hx8k FPGA, and i didn't even start to optimise it (and yet timing analysis says it runs at over 70MHz!): Info: Device utilisation: Info: ICESTORM_LC: 345/ 7680 4% Info: ICESTORM_RAM: 4/ 32 12%
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