I am puzzled by enthusiasm for various species of memory tagging, such as https://www.sifive.com/blog/sifive-shield-an-open-scalable-platform-architecture …, https://www.dovermicrosystems.com/solutions/coreguard/ …, https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/enhancing-memory-safety …, which provide either coarse-grained or statistical protection when there's CHERI, which is fine-grained and exact. 1/2
Well maybe you should broaden your scope a bit and look beyond memory safety? For instance, how does CHERI enforce a policy for a mission critical system such that X can never happen before Y?