WikiChip

@WikiChip

The official WikiChip Twitter account. Hardware (logic), computer architectures, & semiconductor engineering. Technical.

Vrijeme pridruživanja: studeni 2016.

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  1. 3. velj

    Just two months after launch, Intel axes Nervana neural processors.

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  2. 24. sij

    A look at Centaur’s new server-class x86 SoC with an integrated neural processor designed for on-chip inference acceleration in the data center.

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  3. 22. sij

    ASML saw a strong fourth-quarter in 2019 thanks to a large EUV shipment with the production of NXE:3400C machines ramping up. 26 EUV machines shipped in 2019 with 35 more expected for 2020. Backlog continues to grow.

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  4. 19. sij

    Integrated photonics has long been considered a holy grail for processor communication. Ayar Labs TeraPHY represents a major step forward through the co-packaging of optical I/F with the SoC. First product is an Intel Stratix 10 FPGA with 2 SiPho chiplets.

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  5. 17. sij

    7 nm contributes the lion's share of wafer revenue to TSMC's fourth-quarter driven by growth from smartphones and . The foundry is also preparing the 5-nanometer node for early this year and the 6 nm by the end of the year.

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  6. 12. sij

    A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.

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  7. 9. sij

    AMD launches new value and entry-level mobile processors, codenamed Dali.

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  8. 5. sij

    A look at a Bunch of Wires (BoW), a new open standard chiplets interconnect being proposed by the OCP ODSA group intended for standard organic multi-chip packages as a cheaper alternative to silicon interposers and bridges.

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  9. 4. sij

    Jumping ahead of emerging trends, the OCP makes a push for an open and standardized chiplet interface and marketplace with a the Open Domain-Specific Architecture subgroup.

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  10. 15. pro 2019.

    A look at Habana's Goya and Gaudi, two architectures for inference and training designed for the acceleration of data center workloads.

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  11. 14. pro 2019.

    TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

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  12. 13. pro 2019.

    UMC says it has started rolling out its 22-nanometer process, offering a new lower-power and cost-sensitive migration path from its existing 40nm and 28nm nodes.

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  13. 12. pro 2019.

    Zhaoxin unveiled plans for two new x86 SoC designs: a high-performance server chip with up to 32 cores and a separate 7 nm mobile and desktop SoC.

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  14. 10. pro 2019.

    Intel's process technology roadmap reveals decade-out plans, including a future 10nm+++ node and a 1.4nm node heading into 2029.

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  15. 9. pro 2019.

    Centaur lifts the veil on CNS, its next-generation high-performance x86 core for data center and edge computing. The new core also adds support for the AVX-512 extension.

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  16. 6. pro 2019.

    Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration in the data center with four initial models in three different form factors.

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  17. 30. stu 2019.

    NEC refreshes its SX-Aurora Vector Engine accelerator cards with Type 10E models, adopts AMD processors, and outlines roadmap.

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  18. 24. stu 2019.

    Japanese AI Startup Preferred Networks is developing its own custom training chip for its own internal R&D. With a peak compute of half-petaFLOPS per chip, PFN is planning a 2 exaFLOPS (HP) supercomputer.

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  19. 21. stu 2019.
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  20. 17. stu 2019.

    Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel's first Xe GPGPU for HPC, 7nm Ponte Vecchio.

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