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Prikvačeni tweet
We are very proud to present you with the new release of Luma3DS, v10.0! NTP client, blue light filters, lots of cheat engine improvements, many new debugger features, and more! Check it out at https://github.com/AuroraWright/Luma3DS/releases/tag/v10.0 … !
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for spinlocks, should non-temporal (prfm pstl1strm) or temporal (prfm pstl1keep) store-prefetches be used?
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Tux proslijedio/la je Tweet
We're slowly getting back on track... coming soon ( ͡° ͜ʖ├┬┴┬┴pic.twitter.com/4kp6fMBN8f
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Guess which part of the reference manual qemu's generic TLB impl isn't compliant with? :^)pic.twitter.com/eXCkgdZ8zL
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(assuming only one guest, guest has all cpus, no security considerations -- basically in my case EL2 would just be a debugger)
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Hm, so what's the way to *properly* copy guest (EL1) memory into the hypervisor, knowing EL1 and EL2 have different translation regimes (and thus different attributes for the same regions ...) but the same caches? Is it to copy PAR.ATTR to the MAIR & map the page each time?
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I'm referring to https://events.static.linuxfound.org/sites/events/files/slides/slides_10.pdf … and http://events17.linuxfoundation.org/sites/events/files/slides/slides_17.pdf … which make the matter very clear (the latter has very clear diagrams in annex exposing what can go wrong)
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Thankfully this svc has never been made accessible on retail
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Multiple Arm slides in Linux events: cache maintenance by set/way is dangerous, breaks virtualization, breaks cache coherency; should only be used for CPU power on/off no one: Nintendo: implements svcFlushEntireDataCache which does DC CISW (only on the current core)
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oh TVAL existing means having a bit to trap CNTPCT separately is useless because one can just retrive its actual value by writing n to TVAL and computing CVAL-n, henceforth bypassing the hypervisor
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me: why does Nintendo always write cntp_el0+timeout to CVAL instead of directly writing to timeout to TVAL? arch. reference manual: Bits[63:32] RES0, "TimerValue is treated as a signed 32-bit integer" yikes
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"Normal" kernels (e.g. linux): *uses virtual Armv8 timer registers* Switch kernel: *accesses physical timer directly, uses virtual timer regs are extra scratch regs for crashes* ffs
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Tux proslijedio/la je Tweet
For those who would like to check it out, here is the ropchain implementation of LazyPixie that I presented in my talk at
#36c3https://github.com/MrNbaYoh/cecd-lazypixie …Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Have the arm11 post-exploitation + arm9 + arm9 post exploitation payload too:https://github.com/TuxSH/LazyPixie-safehax …
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Hey guys here's my kernel exploit (+ pov) writeup
@MrNbaYoh talked about in his talk:https://github.com/TuxSH/LazyPixieHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Welp I watched
#PROMARE for the 4th time last SaturdayHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
When you meme without memeing at the same time
#GeneralElectionResultshttps://twitter.com/NintendoUK/status/1205457566953816065 …
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