Do you think this version of TSX will be good to implement GHC STM on top of? //cc @stdlib
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Haskell STM semantics are richer than TSX; the impl is like a database (e.g nested transactions). TSX more changes the cost profile of e.g file grained locks with short critical sections, provides lock elision, etc
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Oh, I guess it was Haswell and Broadwell with the bugs! My memory is getting worse :(
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Technically it is enabled in the Skylake i5 and i7 overclockable K SKUs (and newer K SKUs). I suspect Intel might want to keep it as a segment differentiation feature.
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That sounds very decent. Are they on Ryzen yet? Any RISK ARM equivalent or have I got the wrong end of the stick here Tim? ?
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SKX, I presume? Do they finally work?
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"Frequent transactional aborts cause wasted cycles." Cue the new core tech job specs of experience optimising for transactional commit misses! ^_^
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Still waiting for phase RAM. Intel continues to sit on it. ):
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Have ore isn't allowed to use?
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