Yes, 65816 is one example, and the 6502 did it for indirect address calculation.
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Oh, another more extreme example. Pentium 4 had a double-pumped 16-bit ALU. So it was running at a ridiculous clock rate...
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The VLIW4/VLIW5 Radeons evaluated x,y,z,w sequentially, and this allowed them to do horizontal adds/dots "for free".
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maybe
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Does the complexity of pulling it off make for a better/faster chip? It seems you would need HW for a special case not used often.
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this approach is often found in ultra-low-power & ulta-low-energy applications
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CORDIC instructions usually generate ~1 bit at a time & are often pipelined: http://www.sciencedirect.com/science/article/pii/0045790678900307 …
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related: it's common for ultra-low-power MCUs to operate on data 1 bit at a time http://www.ti.com/lsds/ti/microcontrollers-16-bit-32-bit/msp/overview.page … http://rakeshk.crhc.illinois.edu/islped_16_cam.pdf … ...
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