Here is a great academic paper elaborating on asymmetric synchronization: https://www.cs.tau.ac.il/~mad/publications/asplos2015-tbtso.pdf …
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Er... you don't need this on x86. Writes are visible the instant they're done (arguably before, since the line must be in M or E for the write to even happen, which means the core must own it and nobody else can).
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On x86, this enables one heavyweight operation to establish an epoch and ensure that all threads running lightweight operations have recognized on it, without those lightweight operations using slow interlocked atomics - important if there are 100M’s per second of the later.
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Same mechanism for expedited membarrier even, IIUC.
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IPI sounds still quite heavyweight, as in more than any cache coherency protocol would probably cost.
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