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TimSweeneyEpic's profile
Tim Sweeney
Tim Sweeney
Tim Sweeney
@TimSweeneyEpic

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Tim Sweeney

@TimSweeneyEpic

Epic Games founder & CEO

epicgames.com
Joined August 2013

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    1. Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
      • Report Tweet
      • Report NetzDG Violation
      Replying to @tom_forsyth

      CMPXCHG = 18 clocks, no ILP, so 100x slower than a non-atomic operation. And this is stupid, as some CPU architecture improvements could make uncontended atomics much faster.

      1 reply 0 retweets 0 likes
    2. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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      Replying to @TimSweeneyEpic

      Could they? Excellent. Drop me a line, I'll add them.

      1 reply 0 retweets 3 likes
    3. Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
      • Report Tweet
      • Report NetzDG Violation
      Replying to @tom_forsyth

      Please educate me on how write-buffers are implemented and whether adding a ROP is a feasible idea? I mean, if it's just a queue of (address,size,data), then adding an operation wouldn't be hard, and the hardware for add/or/xor/and ROPs would be minimal.

      1 reply 0 retweets 1 like
    4. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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      Replying to @TimSweeneyEpic

      Right, but if you allow it to go out of order with other memory operations, you just broke all the code - coz they're not barriers any more. And if you don't then hey - it stalls.

      1 reply 0 retweets 2 likes
    5. Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
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      Replying to @tom_forsyth

      For many common operations, atomicity is vital but order is not: - ORing a shared bitmask, a common technique used by concurrent garbage collectors. - Increasing or decreasing a reference count without checking its value - Adding to a shared counter

      2 replies 0 retweets 1 like
    6. Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
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      Replying to @TimSweeneyEpic @tom_forsyth

      More simply put, I can atomically MOV [BYTE PTR eax],IMM without LOCK but I cant atomically set bits that way. I see no fundamental reason why, if the CPU supports the former, it can’t economically support the later.

      2 replies 0 retweets 0 likes
    7. Dan Baker‏ @dankbaker 9 Jul 2018
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      Replying to @TimSweeneyEpic @tom_forsyth

      You could probably build special hardware to pipeline atomics to specific memory locations, but generally you have to read/write an entire cache line at a time, so that piece of memory has to be locked while you do that

      1 reply 0 retweets 0 likes
    8. Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
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      Replying to @dankbaker @tom_forsyth

      Please bear with me on this: There's currently a piece of hardware that can atomically write just 1 byte into a 64-byte cache line. So clearly it's transforming (old cache line, write request) -> (new cache line). QUESTION: What is this hardware, and can it not support a ROP?

      5 replies 0 retweets 0 likes
    9. bb‏ @brrrianb 9 Jul 2018
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      Replying to @TimSweeneyEpic @dankbaker @tom_forsyth

      I think atomic RMW is the reason for locking the line, using LL/SC loop, or atomic RMW instruction. If you just write, with a literal value, fine. But if value came from memory, need to ensure it wasn’t modified by other bus master while <op> and store exec.

      2 replies 0 retweets 0 likes
    10. bb‏ @brrrianb 9 Jul 2018
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      Replying to @brrrianb @TimSweeneyEpic and

      Is there any good explanation on what a ROP does and how it is designed in hardware?

      2 replies 0 retweets 0 likes
      Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
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      Replying to @brrrianb @dankbaker @tom_forsyth

      https://en.m.wikipedia.org/wiki/Render_output_unit … Generally, a ROP is a simple ALU that operates asynchronously at the end of the computing pipeline to merge its output into memory without stalling the front-end.

      11:13 PM - 9 Jul 2018
      0 replies 0 retweets 0 likes

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