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TimSweeneyEpic's profile
Tim Sweeney
Tim Sweeney
Tim Sweeney
@TimSweeneyEpic

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Tim Sweeney

@TimSweeneyEpic

Epic Games founder & CEO

epicgames.com
Joined August 2013

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    1. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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      Replying to @TimSweeneyEpic

      The question is whether they're slow because they're actually contesting or not. IIRC they're about 20-30 clocks if uncontested and the data's in the cache? Deferring the update breaks the whole ordered memory thing, which is like - the whole point of doing the LOCK!

      3 replies 0 retweets 1 like
    2. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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      Replying to @tom_forsyth @TimSweeneyEpic

      What I mean is - the whole point of the LOCKed instruction is usually to say "I own this data now". If you defer it and allow updates to proceed, then... you just broke the code!

      1 reply 0 retweets 0 likes
    3. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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      Replying to @tom_forsyth @TimSweeneyEpic

      Now you could defer ALL the updates (locked and not), and that's what TSX/HLE basically does. And it's really difficult and scary and there's lots of caveats!

      2 replies 0 retweets 0 likes
    4. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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      Replying to @tom_forsyth @TimSweeneyEpic

      So you have to fit your entire state update inside a "ROP packet" or similar, which is a bit of a limited circumstance. Note that you can actually do this - make a thread that is the "ROP" unit and have other threads send it update packets, and it applies the packets in order.

      1 reply 0 retweets 1 like
    5. Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
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      Replying to @tom_forsyth

      Write buffers store (address,value) already - both up to 64 bits. Couldn't we easily add a ROP byte? Semantics are clean for ADD, OR, AND, XOR, etc.

      1 reply 0 retweets 0 likes
    6. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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      Replying to @TimSweeneyEpic

      Well, you can do any 64-bit operation you like by wrapping it in CMPXCHG.

      1 reply 0 retweets 0 likes
    7. Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
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      Replying to @tom_forsyth

      CMPXCHG = 18 clocks, no ILP, so 100x slower than a non-atomic operation. And this is stupid, as some CPU architecture improvements could make uncontended atomics much faster.

      1 reply 0 retweets 0 likes
    8. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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      Replying to @TimSweeneyEpic

      Could they? Excellent. Drop me a line, I'll add them.

      1 reply 0 retweets 3 likes
    9. Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
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      Replying to @tom_forsyth

      Please educate me on how write-buffers are implemented and whether adding a ROP is a feasible idea? I mean, if it's just a queue of (address,size,data), then adding an operation wouldn't be hard, and the hardware for add/or/xor/and ROPs would be minimal.

      1 reply 0 retweets 1 like
    10. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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      Replying to @TimSweeneyEpic

      Right, but if you allow it to go out of order with other memory operations, you just broke all the code - coz they're not barriers any more. And if you don't then hey - it stalls.

      1 reply 0 retweets 2 likes
      Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
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      Replying to @tom_forsyth

      For many common operations, atomicity is vital but order is not: - ORing a shared bitmask, a common technique used by concurrent garbage collectors. - Increasing or decreasing a reference count without checking its value - Adding to a shared counter

      1:24 PM - 9 Jul 2018
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        2. Tim Sweeney‏ @TimSweeneyEpic 9 Jul 2018
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          Replying to @TimSweeneyEpic @tom_forsyth

          More simply put, I can atomically MOV [BYTE PTR eax],IMM without LOCK but I cant atomically set bits that way. I see no fundamental reason why, if the CPU supports the former, it can’t economically support the later.

          2 replies 0 retweets 0 likes
        3. Dan Baker‏ @dankbaker 9 Jul 2018
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          Replying to @TimSweeneyEpic @tom_forsyth

          You could probably build special hardware to pipeline atomics to specific memory locations, but generally you have to read/write an entire cache line at a time, so that piece of memory has to be locked while you do that

          1 reply 0 retweets 0 likes
        4. 4 more replies
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        2. Tom Forsyth‏ @tom_forsyth 9 Jul 2018
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          Replying to @TimSweeneyEpic

          Those are certainly interesting use cases. I know we kicked around the ROP idea for KNF+KNC. It's pretty complex, and of course totally destroys the x86 memory model. In the end we decided that making a "ROP thread" was the better way - especially since we had 4 threads per core.

          1 reply 0 retweets 0 likes
        3. Timo Heinäpurola‏ @heinapurola 9 Jul 2018
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          Replying to @tom_forsyth @TimSweeneyEpic

          Adding features that walk the borders of the core architecture are always dangerous to say the least. This also applies to higher level software, which is why for production code it’s usually better to choose the slightly slower path but that is the more reliable one

          0 replies 0 retweets 0 likes
        4. End of conversation

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