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This schematic is my personal white whale at this point. It all kicks off when /DRQ is pulsed low. Based on the crapfest of analog conditioning circuitry on other pages, STC starts pulsing, incrementing the 74HC4040. Once the pulses taper off based on pen distance, STC pulses.pic.twitter.com/Xztxy39zht
Presumably, the 12-bit ripple counter counts the number of pulses received before it tapers off. But when and for how long does /IRQ get pulled low, and what releases it back high again?
![[ColeJ]](https://pbs.twimg.com/profile_images/1043000626056065024/vDRPnUpt_normal.jpg)
It seems like /DRQ must be followed by a pulse on STC. That will latch the high bit on RSTOP from IC17, and that high bit will go through IC15 generating the /IRQ when SPC triggers. That IRQ can only be cleared by pulling /DRQ low again, preparing for the next round.
So in other words, /DRQ is probably the last operation in a read cycle, not the first.
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