I've got all of the SPARCstation 2's cache diagnostics passing. Now I'm on to the FPU diagnostics, which are even more brutal. I swear these tests were the product of a brilliant, but sick, mind.
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But FP insns happen asynchronously. The IU will move right on to the store insn, but since the store source is the in-flight FP reg, the CPU will interlock on the FPU during execution. The zero-divide exception hits, then the exception handler returns to the instruction after it.
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So as a hack, let's still advance the program counter despite a pending FP exception. Great, two more self-tests pass. Now the "FPU Exception and Misalignment Test" fails - *because* there's a divide-by-zero exception. Why? I'll tell you why.
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Misaligned stores are detected during the decode stage. So while the FPU is asynchronously gearing up for a divide-by-zero exception, the IU fetches the store insn, decodes it, and triggers a misalignment exception.
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So now I pretty much *need* to make the FPU execution in MAME's SPARC core occur asynchronously. And handle FP register interlocks. Oh, what a lovely tea party.
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