also cc: @andreif7
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They say they used a new "logically tagged directory" cache design. I have heard of this but only in the literature. Like I said, this is IBM, so but of course
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IBM zArch “logical” is what the rest of the world calls virtual. Terminology issues...
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Nope - not just that - read the slides, they integrated the TLB into a single structure with a new directory lookup. So it's not /just/ VIVT how everyone else does it. They need to prevent conflicting tags, seems they do this by also factoring the AS ID into the new dir design
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That does not solve all problems... Aliasing can still occur..
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Indeed. They must have solved this. More weekend reading...
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Older AMDs accepted aliasing afaik... It just means performance penalties for some cases... So it is a trade of between these cases and others that would benefit from the larger cache size...
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I never understood why most CPUs don't just deal with aliasing in hardware anymore, except smaller ARM cores. Don't you just have to check for aliases on line fills? Does this make pipelining harder or something?
End of conversation
New conversation -
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