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I’d love a blogpost written from the perspective of a chipmaker - Why this issue exists. I’d never question their competency, but it seems like a violation of expectations in hindsight. Based on my very limited understanding of these issues.
Update: It appears Linus is also confused on why this is expected behavior.https://twitter.com/TheRegister/status/948727914312298496 …
https://lkml.org/lkml/2018/1/3/797 … pic.twitter.com/Go02sQUN621) Vulnerability to cache timing attacks wasn't part of "correctness" criteria when this stuff was designed. 2) [For Intel] doing the access check in parallel with sequential execution saves time, with no "observable" effect if you ignore 1).
My gut says the desire for speed lead to someone choosing the fast path over the safe one, hence why AMD isn't as susceptible.
So I wrote a blog post that hopefully answers your question. It's kinda vague, so hit me for followup questions.
This is the best single-tweet summary ICYMIhttps://twitter.com/rsthau/status/948740076091203585 …
oh and BTW @Metlstorm is going to love the typo in your other blog post titlepic.twitter.com/c9A9JAKTqt
Mettle-down!
http://ieeexplore.ieee.org/document/288304/?reload=true … This is decades old technology, literally older than SQL injection. Until someone stopped and said 'wait a minute', entirely predictable that it'd keep getting carried forward and refined, because to many, it had quite literally always been a thing.
The simple answer is that it's "correct" behavior according to their definition of "correct". There is not bug.
Literally nobody realized. That’s it. People considered impact of speculative and OOO execution, and put rollbacks in place, but nobody ever considered the impact on cache timing. Same thing as with every timing sidechannel ever.
Core issue is optimizing for performance over all else. Would be interesting to study the origin of the performance culture.
Performance and safety aren't mutually exclusive things, it just requires a hell of a lot more work to get it right 
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