Finished my Claybook raw->typed buffer port. Here's a thread containing some performance analysis numbers on AMD GPU. TLDR: Use raw buffers if your platform supports them!
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Particle sim P1 (integrator): Typed buffers double the number of loads/stores, because Typed UAV load limitation forces in-place update to single channel uint32/float32. However this pass is fully mem bound -> no perf impact of added mem instructions.
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Shape match reduction: This pass loses some scalar optimizations (typed buffers aren't scalar optimized). VGPR count = +4. Increased number of narrow typed loads is a big perf impact, because this pass loads all particles twice. 40% slower with typed buffer.
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Physics sim pass 2 (apply shape match, collisions, deform): Huge +16 VGPR cost (64 -> 80) because of lost scalar opts (typed buffer's can't be scalar optimized). 2x load/store count (typed UAV load limit). Fortunately this shader is fully memory bandwidth bound. Only 3% slower.
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Particle mesh prepare (offload from VS): +4 VGPR because of lost scalar opts. Loads 4x particle neighbors to calculate normal/tangent. Lots of extra loads because of typed UAV load limitations. Part positions are 4x16b = Load2 (or 2x typed R32 load). BW bound -> only 8% slower.
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Fluid sim (pressure calc pass): +8 VGPR because of lost scalar optimizations. Other fluid sim passes seem fine. Fluid sim passes are fully async compute overlapped with rendering, so exact perf analysis is not possible.
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Added VGPRs and higher VMEM issue rate isn't as much a problem as I expected for passes without async compute overlap. These things are a bigger problem with async compute overlap. Fortunately I don't need to use typed buffer code path on platforms that benefit greatly from async
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Optimization possibility: Use R32G32_UINT read only view (SRV) for shape match reduction pass and render setup pass, because these passes write output to a separate buffer. Typed UAV load format limitation is not an issue in these cases.
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You are allowed to create multiple raw/typed views to the same buffer with different element bit depths. This trick is not legal for textures. Texture views must have equal bit depth to the typeless format of the resource. Also structured buffer's don't support typed/raw views.
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Also worth noting that simultaneous SRV (read) and UAV (write) binding to same resource is not allowed. DX11 will automatically unbind one of them in this case. You can't use this to avoid the typed UAV load issue.
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To make things clear: Claybook will continue to use raw buffers on PC and all GCN based consoles.
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Raw buffers are the best choice for AMD (all GCN generations). Nvidia has nowadays (Volta/Turing) also very fast raw buffers (faster than typed):
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My raw buffer benchmark measures throughput. I would guess that Volta/Turing has lower latency for raw loads too. 28 cycle L1$ measured latency (in CUDA) is just crazy good. See page 19 of this presentation: arxiv.org/pdf/1804.06826
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