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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Rich Felker‏ @RichFelker Apr 2
      Replying to @ErrataRob @travisgoodspeed @Cloudflare

      I've seen similar results on big compile jobs, no acceleration. Need to test myself sometime.

      1 reply 0 retweets 0 likes
    2. Rich Felker‏ @RichFelker Apr 2
      Replying to @RichFelker @ErrataRob and

      My semi-educated guess is that you can do way better than 1/2 power consumption (maybe as low as 10%) just by using a larger array of simpler cores rather than higher-end out-of-order ARMs.

      2 replies 0 retweets 0 likes
    3. Robᵉʳᵗ Graham X🅂 Max‏ @ErrataRob Apr 2
      Replying to @RichFelker @travisgoodspeed @Cloudflare

      Yes, for some applications (like the network processing CloudFlare does). But for most tasks, the coordination among cores quickly overcomes the benefits of many cores. That's why Sun failed with their SPARC T-1 strategy.

      2 replies 0 retweets 0 likes
    4. Rich Felker‏ @RichFelker Apr 2
      Replying to @ErrataRob @travisgoodspeed @Cloudflare

      Personally my only use for cpu perf is big compile jobs, which are (modulo awful recursive-configure scripts) 100% //izable and don't share data. But yeah it varies with what you're doing.

      1 reply 0 retweets 0 likes
    5. John Regehr‏ @johnregehr Apr 2
      Replying to @RichFelker @ErrataRob and

      I'm in a similar boat (also want SMT solvers, but their execution characteristics seem roughly similar to compilers, but more memory-bound).

      1 reply 0 retweets 1 like
    6. John Regehr‏ @johnregehr Apr 2
      Replying to @johnregehr @RichFelker and

      seems like the keys are memory bandwidth and huge last-level cache. so far an ARM farm doesn't do anything for me, but I haven't got hold of a Thunder X2 box yet.

      1 reply 0 retweets 0 likes
    7. Robᵉʳᵗ Graham X🅂 Max‏ @ErrataRob Apr 2
      Replying to @johnregehr @RichFelker and

      My suspicion is that for memory-bandwidth constrained tasks that CPUs designed to go to sleep faster (and not consume power) will be more power efficient.

      2 replies 0 retweets 0 likes
    8. John Regehr‏ @johnregehr Apr 2
      Replying to @ErrataRob @RichFelker and

      yeah, I don't know. but I do know that for various reasons there's a minimum single-core power that I want, and that ARMs by and large haven't reached it.

      1 reply 0 retweets 0 likes
    9. John Regehr‏ @johnregehr Apr 2
      Replying to @johnregehr @ErrataRob and

      minimum single-core instruction throughput I mean

      1 reply 0 retweets 0 likes
    10. John Regehr‏ @johnregehr Apr 2
      Replying to @johnregehr @ErrataRob and

      even if I'm doing nothing other than compiling, I want a 16-way Xeon instead of a 600-way Raspberry Pi in other words

      2 replies 0 retweets 0 likes
      Rich Felker‏ @RichFelker Apr 2
      Replying to @johnregehr @ErrataRob and

      Well, you could have some sort of big.LITTLE arrangement so that make runs blazing fast when only <=N files have changed for some small N... :-)

      3:10 PM - 2 Apr 2018
      1 reply 0 retweets 0 likes
        1. New conversation
        2. Robᵉʳᵗ Graham X🅂 Max‏ @ErrataRob Apr 2
          Replying to @RichFelker @johnregehr and

          There's a lot of criticism of the big.LITTLE approach, with many feeling it's still just better having a faster core getting work done sooner being able to sleep longer.

          1 reply 0 retweets 0 likes
        3. CopperheadOS‏ @CopperheadOS Apr 2
          Replying to @ErrataRob @RichFelker and

          The weaker cores are usually a substantially more efficient design, not just lower clocked variants of the main cores. Battery life is much better with all the big cores disabled than all LITTLE ones and devices with only those more efficient cores get much better battery life.

          1 reply 0 retweets 1 like
        4. CopperheadOS‏ @CopperheadOS Apr 2
          Replying to @CopperheadOS @ErrataRob and

          Qualcomm 845 uses 4x modified Cortex-A75 (https://en.wikipedia.org/wiki/ARM_Cortex-A75 …) and 4x modified Cortex-A55 which are in-order (https://en.wikipedia.org/wiki/ARM_Cortex-A55 …). It works quite well with the current energy aware scheduler implementation. It would be terrible with the mainline Linux kernel scheduler.

          0 replies 0 retweets 0 likes
        5. End of conversation

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