Once again, @ErrataRob derails my brilliant plan to build an MSP430 workstation and server platform.https://twitter.com/ErrataRob/status/980907462973902849 …
My semi-educated guess is that you can do way better than 1/2 power consumption (maybe as low as 10%) just by using a larger array of simpler cores rather than higher-end out-of-order ARMs.
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Of course if Intel made simple cores they could be competitive here too, but they abandoned the Atom microarchitecture that was the closest thing they had (and likely their only hope for making chips unaffected by Spectre).
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I want to see a server using a Xeon Phi (72 Atom cores) do a Linux compile. The massive floating point logic may make things inefficient, but it'd still be fun to try.
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Wow interesting. I had no idea Larrabee was non-OOOE. I might have to pick one up as a better Spectre-free option than the S1260 I've got now.
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That's the old stuff. The latest (Knight's Landing) is OoO, using the newer Airmont cores that are OoO. It turns out that some OoO is still more power efficient than none at all.
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Right, but I specifically want non-OOOE. Thus looking at old stuff.
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Sadly it looks like the old stuff was never produced in significant commercial quantities...
End of conversation
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Yes, for some applications (like the network processing CloudFlare does). But for most tasks, the coordination among cores quickly overcomes the benefits of many cores. That's why Sun failed with their SPARC T-1 strategy.
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Also, Cavium has been doing this forever (MIPS, but changed to ARM recently) and they've only gotten traction in the network appliance market, despite many attempts at servers.
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Well MIPS was a huge incoherent mess of incompatible ABIs, wrong ABIs (32-bit time_t on n32), secretly-incompatible ISA variants (mipsr6), ... with no hope of gaining traction as a platform.
End of conversation
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