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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Jan Gray‏ @jangray Mar 10

      Jan Gray Retweeted whitequark

      “A microprocessor is just a crazy Rube Goldberg machine for wigglin’ DRAM pins” -- me I have no problem with a high level ANDF and a low level ISA. I do not care for the memory-memory ISA the authors consider. I think it is a wasteful (= untenable) HW-SW interface.https://twitter.com/whitequark/status/972481055688155139 …

      Jan Gray added,

      whitequark @whitequark
      "This Architecture Tastes Like Microarchitecture", a very curious paper that offers a fresh look on ISA abstractions http://wp3workshop.website/pdfs/WP3_dunham.pdf … pic.twitter.com/c380MtgdsM
      4 replies 2 retweets 10 likes
      Show this thread
    2. Jan Gray‏ @jangray Mar 10

      The law of energy efficiency inevitability: the more energy effficient way will displace the less efficient way — eventually.

      1 reply 0 retweets 2 likes
      Show this thread
    3. Jan Gray‏ @jangray Mar 10

      Don’t spend hardware resources and energy rediscovering invariants, dependencies, names, schedules, probabilities that the compiler/software stack already know.

      1 reply 1 retweet 1 like
      Show this thread
    4. Jan Gray‏ @jangray Mar 10

      For example in the case or GRVI Phalanx, special purpose PEs running small kernels, I think it is a good idea to augment the base @risc_v with area/energy efficient perf hacks such as branch delay slots which cost ~0 HW and improve IPC.

      1 reply 0 retweets 0 likes
      Show this thread
    5. Jan Gray‏ @jangray Mar 10

      Before I am pilloried for my comp.arch apostasy note this has no impact on RV32I etc as an enduring stable standard interchange format. Just somewhere between linker and HW something might rewrite bits of the binary to improve perf/efficiency.

      2 replies 0 retweets 1 like
      Show this thread
    6. Rich Felker‏ @RichFelker Mar 10
      Replying to @jangray

      This is a horrible idea. Violating ISA stability for any reason, much less minuscule performance hacks, is catastrophic for the value of the ISA as a platform.

      1 reply 0 retweets 1 like
    7. Jan Gray‏ @jangray Mar 10
      Replying to @RichFelker

      1. Haven’t done this yet. 2. No impact on RV32I. 3. In context of FPGA accelerator soft processors with extensible ISAs (custom FUs, etc.) perfectly normal. 4. Depending upon how debugging a kernel works, TBD, may not be visible. 5. Think of it as JIT’d microcode. Better? :-)

      2 replies 0 retweets 0 likes
    8. Rich Felker‏ @RichFelker Mar 10
      Replying to @jangray

      The impact is perception (a fragmented ISA) and risk of widespread use (actual fragmentation).

      1 reply 0 retweets 1 like
      Rich Felker‏ @RichFelker Mar 10
      Replying to @RichFelker @jangray

      Think also of how tooling is affected. Either upstream crap to support this, or ancient forks of the tooling kept around to support it.

      12:51 PM - 10 Mar 2018
      • 1 Like
      • Jan Gray
      1 reply 0 retweets 1 like
        1. Jan Gray‏ @jangray Mar 10
          Replying to @RichFelker

          Yes, either the tooling has to deal with it (bad whether upstreamed or forks, as you say) or something has to keep two sets of books (may be easier). (In any case tooling will be extensible to deal with ISA extensions.)

          0 replies 0 retweets 0 likes
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