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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Rich Felker‏ @RichFelker Feb 21

      Rich Felker Retweeted Pumpkin Fright 👨‍⚕️ 🍕

      As expected, silence on Spectre v1. But nice job @arstechnica being explicit that the microcode fixes are for Spectre v2.https://twitter.com/DrPizza/status/966389985510416385 …

      Rich Felker added,

      Pumpkin Fright 👨‍⚕️ 🍕Verified account @DrPizza
      Intel ships (hopefully stable) microcode for Skylake, Kaby Lake, Coffee Lake https://arstechnica.com/?p=1263653 
      3 replies 0 retweets 1 like
    2. Pumpkin Fright 👨‍⚕️ 🍕‏Verified account @DrPizza Feb 21
      Replying to @RichFelker @arstechnica

      I think v1 is going to pretty universally require application-level fixes.

      1 reply 0 retweets 0 likes
      Rich Felker‏ @RichFelker Feb 21
      Replying to @DrPizza @arstechnica

      An MSR to disable branch predictor should suffice. Need lawyers forcing Intel to do it (and fix the bug in future cpus).

      11:38 AM - 21 Feb 2018
      2 replies 0 retweets 0 likes
        1. New conversation
        2. Pumpkin Fright 👨‍⚕️ 🍕‏Verified account @DrPizza Feb 21
          Replying to @RichFelker @arstechnica

          So you want to end all speculation past a cmp?

          2 replies 0 retweets 0 likes
        3. Rich Felker‏ @RichFelker Feb 21
          Replying to @DrPizza @arstechnica

          Until there's hardware to isolate the entire speculative cache hierarchy to be non-observable, YES.

          1 reply 0 retweets 0 likes
        4. Pumpkin Fright 👨‍⚕️ 🍕‏Verified account @DrPizza Feb 21
          Replying to @RichFelker @arstechnica

          No, except for SGX, there is no architectural protection domain here. A process is allowed to observe its own cache misses.

          0 replies 0 retweets 0 likes
        5. End of conversation
        1. New conversation
        2. Danny Davos‏ @io_r_us Feb 21
          Replying to @RichFelker @DrPizza @arstechnica

          V4 is making any existing fix strategies arguable.

          1 reply 0 retweets 0 likes
        3. Rich Felker‏ @RichFelker Feb 21
          Replying to @io_r_us @DrPizza @arstechnica

          Can you elaborate?

          1 reply 0 retweets 0 likes
        4. Danny Davos‏ @io_r_us Feb 21
          Replying to @RichFelker @DrPizza @arstechnica

          Just echoing the paper "Where Meltdown and Spectre arise by polluting the cache during speculation, MeltdownPrime and SpectrePrime are caused by write requests being sent out speculatively in a system that uses an invalidation-based coherence protocol." https://arxiv.org/pdf/1802.03802.pdf …

          1 reply 1 retweet 1 like
        5. Pumpkin Fright 👨‍⚕️ 🍕‏Verified account @DrPizza Feb 21
          Replying to @io_r_us @RichFelker @arstechnica

          That paper is using the exact same speculative execution, it's just doing the inverse cache side channel (one line is fast, because it's been fetched, rather than slow, because it's been evicted)

          1 reply 0 retweets 2 likes
        6. Danny Davos‏ @io_r_us Feb 21
          Replying to @DrPizza @RichFelker @arstechnica

          Not sure what you mean ... novel in that they are 2-core attacks which leverage the cache line invalidation mechanism in modern cache coherence protocols. ... Prime attacks exploit invalidation-based coherence protocols ... same level of precision as a Flush+Reload attack

          1 reply 0 retweets 1 like
        7. Pumpkin Fright 👨‍⚕️ 🍕‏Verified account @DrPizza Feb 21
          Replying to @io_r_us @RichFelker @arstechnica

          I mean that they're using the exact same speculative execution, just slightly different cache side channels. The original papers used flush+reload (which makes one loaded line fast), this is using prime+probe (which makes one invalidated line slow).

          1 reply 0 retweets 1 like
        8. Pumpkin Fright 👨‍⚕️ 🍕‏Verified account @DrPizza Feb 21
          Replying to @DrPizza @io_r_us and

          In both cases, if you prevent speculative loads (e.g. with x86 lfence, ARM csdb), the only cache lines that get loaded or invalidated are those that are actually used.

          1 reply 0 retweets 1 like
        9. Pumpkin Fright 👨‍⚕️ 🍕‏Verified account @DrPizza Feb 21
          Replying to @DrPizza @io_r_us and

          Observable cache effects of the path-actually-taken are a problem for cryptography, but they're not a problem for speculative execution side channels.

          0 replies 0 retweets 1 like
        10. End of conversation

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