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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Watson Ladd‏ @WatsonLadd Jan 27
      Replying to @siddhesh_p @RichFelker and

      You can read the results from L3 cache of speculation

      1 reply 0 retweets 0 likes
    2. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @WatsonLadd @RichFelker and

      No for 3 reasons:measuring L3 and memory latencies would be error prone given how close they are and I don't think there are instructions to specifically load to L3 to do a flush+reload. Also, evicting from L3 is *way* harder.

      1 reply 0 retweets 0 likes
    3. Watson Ladd‏ @WatsonLadd Jan 27
      Replying to @siddhesh_p @RichFelker and

      Paging @cperciva who did exactly that to attack AES.

      2 replies 0 retweets 0 likes
    4. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @WatsonLadd @RichFelker and

      Interesting. Link to paper?

      1 reply 0 retweets 0 likes
    5. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @siddhesh_p @WatsonLadd and

      Never mind, his blog has links.

      1 reply 0 retweets 0 likes
    6. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @siddhesh_p @WatsonLadd and

      Hmm so it looks like it is feasible to do a side channel attack on the last level of cache. ARM spec does not specify how CPUs handle flushing in hidden cache levels, but assuming it still leaves a channel to snoop on, a parallel speculative cache seems like the best way to go

      1 reply 0 retweets 1 like
    7. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @siddhesh_p @WatsonLadd and

      I'll probably take a while to grok it's feasibility in the speculative execution use case, but I suppose the safer assumption is that it's doable.

      1 reply 0 retweets 0 likes
    8. Rich Felker‏ @RichFelker Jan 28
      Replying to @siddhesh_p @WatsonLadd and

      Yes. I think this means disabling speculative fetch (L1 cache miss) for non-retired address operands is necessary for a fix. Sufficient?

      1 reply 0 retweets 0 likes
    9. Siddhesh Poyarekar‏ @siddhesh_p Jan 28
      Replying to @RichFelker @WatsonLadd and

      That seems sufficient. The branch ought to have been taken at retire.

      1 reply 0 retweets 1 like
    10. Rich Felker‏ @RichFelker Jan 28
      Replying to @siddhesh_p @WatsonLadd and

      Actually I worry it's not sufficient with some branch prediction especially indirect...

      1 reply 0 retweets 0 likes
      Rich Felker‏ @RichFelker Jan 28
      Replying to @RichFelker @siddhesh_p and

      Think case where cpu predicts call to function taking ptr but you're really calling function with integer arg under attacker control.

      8:08 AM - 28 Jan 2018
      2 replies 0 retweets 0 likes
        1. Rich Felker‏ @RichFelker Jan 28
          Replying to @RichFelker @siddhesh_p and

          Disappointing but my guess is that you just have to disable all speculative fetch. At least all future cpus should give an MSR to do that for users who need strong guarantee or don't care about perf loss under heavy L1 misses.

          0 replies 0 retweets 0 likes
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        2. Siddhesh Poyarekar‏ @siddhesh_p Jan 28
          Replying to @RichFelker @WatsonLadd and

          Hmm, so if all speculative execution was done in a hidden cache (not in the regular cache hierarchy) then that wouldn't matter since the side effects wouldn't be visible. Sorry, I just can't get the speculative cache idea out of my head since it seems to fit, just needs tweaking

          1 reply 0 retweets 0 likes
        3. Siddhesh Poyarekar‏ @siddhesh_p Jan 28
          Replying to @siddhesh_p @RichFelker and

          It would double the production cost as far as cache design is concerned since you're splitting each level into a visible and invisible part. But then that should achieve the needed isolation since you can no longer see what's going on during speculation.

          1 reply 0 retweets 0 likes
        4. Watson Ladd‏ @WatsonLadd Jan 28
          Replying to @siddhesh_p @RichFelker and

          How do you make the speculated reads visible to the ordinary cache? And you might not have speculated across one jump: might speculate both ways across multiple jumps, as well as over traps

          1 reply 0 retweets 0 likes
        5. Siddhesh Poyarekar‏ @siddhesh_p Jan 28
          Replying to @WatsonLadd @RichFelker and

          With the disclaimer that this is an imaginary design that has no physical reality associated with it, you have an extra few cycles of latency when you swap in lines from the speculative cache to visible cache when the speculated branch is taken.

          1 reply 0 retweets 0 likes
        6. Siddhesh Poyarekar‏ @siddhesh_p Jan 28
          Replying to @siddhesh_p @WatsonLadd and

          The actually speculation mechanism should not change with this, only the fact that cache population and invalidation for the speculative execution ought to happen in the invisible cache, not the visible cache. Changes committed to visible cache when branch is taken.

          1 reply 0 retweets 0 likes
        7. Watson Ladd‏ @WatsonLadd Jan 28
          Replying to @siddhesh_p @RichFelker and

          Is this similar to TSO maintenance logic? I have no idea. And I still haven't figured out mmmix enough to test perf impacts.

          1 reply 0 retweets 0 likes
        8. Siddhesh Poyarekar‏ @siddhesh_p Jan 28
          Replying to @WatsonLadd @RichFelker and

          I don't know tso or mmix to make a comparison. This is just something I've been thinking idly over while waiting for my builds to finish.

          0 replies 0 retweets 1 like
        9. End of conversation

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