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RichFelker's profile
Rich Felker
Rich Felker
Rich Felker
@RichFelker

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Rich Felker

@RichFelker

Yeah, I do @musllibc, FOSS & infosec stuff. But now is not the time for a mostly-/only-tech Twitter feed.

musl-libc.org
Joined March 2014

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    1. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @WatsonLadd @RichFelker and

      It will impact performance, but not nearly as much as a speculation barrier. E.g. if the CPU hides L3, speculative loads should only happen to L3 and then committed to L2 (and L1 if temporal) on retire. Your additional cost is then limited to L3 latency, not memory latency.

      2 replies 0 retweets 0 likes
    2. Watson Ladd‏ @WatsonLadd Jan 27
      Replying to @siddhesh_p @RichFelker and

      You can read the results from L3 cache of speculation

      1 reply 0 retweets 0 likes
    3. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @WatsonLadd @RichFelker and

      No for 3 reasons:measuring L3 and memory latencies would be error prone given how close they are and I don't think there are instructions to specifically load to L3 to do a flush+reload. Also, evicting from L3 is *way* harder.

      1 reply 0 retweets 0 likes
    4. Watson Ladd‏ @WatsonLadd Jan 27
      Replying to @siddhesh_p @RichFelker and

      Paging @cperciva who did exactly that to attack AES.

      2 replies 0 retweets 0 likes
    5. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @WatsonLadd @RichFelker and

      Interesting. Link to paper?

      1 reply 0 retweets 0 likes
    6. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @siddhesh_p @WatsonLadd and

      Never mind, his blog has links.

      1 reply 0 retweets 0 likes
    7. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @siddhesh_p @WatsonLadd and

      Hmm so it looks like it is feasible to do a side channel attack on the last level of cache. ARM spec does not specify how CPUs handle flushing in hidden cache levels, but assuming it still leaves a channel to snoop on, a parallel speculative cache seems like the best way to go

      1 reply 0 retweets 1 like
    8. Siddhesh Poyarekar‏ @siddhesh_p Jan 27
      Replying to @siddhesh_p @WatsonLadd and

      I'll probably take a while to grok it's feasibility in the speculative execution use case, but I suppose the safer assumption is that it's doable.

      1 reply 0 retweets 0 likes
    9. Rich Felker‏ @RichFelker Jan 28
      Replying to @siddhesh_p @WatsonLadd and

      Yes. I think this means disabling speculative fetch (L1 cache miss) for non-retired address operands is necessary for a fix. Sufficient?

      1 reply 0 retweets 0 likes
    10. Siddhesh Poyarekar‏ @siddhesh_p Jan 28
      Replying to @RichFelker @WatsonLadd and

      That seems sufficient. The branch ought to have been taken at retire.

      1 reply 0 retweets 1 like
      Rich Felker‏ @RichFelker Jan 28
      Replying to @siddhesh_p @WatsonLadd and

      Actually I worry it's not sufficient with some branch prediction especially indirect...

      8:06 AM - 28 Jan 2018
      1 reply 0 retweets 0 likes
        1. New conversation
        2. Rich Felker‏ @RichFelker Jan 28
          Replying to @RichFelker @siddhesh_p and

          Think case where cpu predicts call to function taking ptr but you're really calling function with integer arg under attacker control.

          2 replies 0 retweets 0 likes
        3. Rich Felker‏ @RichFelker Jan 28
          Replying to @RichFelker @siddhesh_p and

          Disappointing but my guess is that you just have to disable all speculative fetch. At least all future cpus should give an MSR to do that for users who need strong guarantee or don't care about perf loss under heavy L1 misses.

          0 replies 0 retweets 0 likes
        4. End of conversation

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