It will impact performance, but not nearly as much as a speculation barrier. E.g. if the CPU hides L3, speculative loads should only happen to L3 and then committed to L2 (and L1 if temporal) on retire. Your additional cost is then limited to L3 latency, not memory latency.
Actually I worry it's not sufficient with some branch prediction especially indirect...
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Think case where cpu predicts call to function taking ptr but you're really calling function with integer arg under attacker control.
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Disappointing but my guess is that you just have to disable all speculative fetch. At least all future cpus should give an MSR to do that for users who need strong guarantee or don't care about perf loss under heavy L1 misses.
End of conversation
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