When people slam CPU manufacturers for Spectre, remember: Customers demanded speed doubling on legacy code, CPU vendors bent over backwards to accomodate programmers that did not want to learn parallelism.
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Replying to @halvarflake
I think this narrative is false. CPU vendors pushed increased speeds to sell more cpus. Demand was a function of supply. There was no need for more speed until sw vendors started writing (super-bloated shit code) to higher-end systems they could assume users had.
3 replies 5 retweets 28 likes -
Replying to @RichFelker @halvarflake
CPUs were plenty fast for desktop/office/web/etc. use 15-20 years ago. Comparable apps run SLOWER on affordable systems now than they did then due to much worse software architectures (giant js apps, etc.).
1 reply 6 retweets 24 likes -
Replying to @RichFelker @halvarflake
Moreover OOOE can be made safe, at low or no perf cost, if you're careful about cache side effects. Vendors traded marginal perf/$ gain for sloppiness that compromised safety.
1 reply 0 retweets 10 likes -
Replying to @RichFelker @halvarflake
Show me. And performance needed for better energy usage, doing more work.
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Replying to @WatsonLadd @halvarflake
Naive approach which likely works (but needs verification): never fetch cache lines speculatively, only speculate with already-in-cache data.
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Replying to @RichFelker @halvarflake
You said minimal performance impact. That won't be true. Hiding latency of cache miss by speculating on addresses crucial
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Tagging cache units with branch IDs and flush as branches become invalid?
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Not unless you can avoid visibility across HT. You need a few hidden speculative-only cache lines per hw thread I suspect.
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But isn’t speculation bound to a core already? Oh what a horror to manage... I feel sorry for those engineers designing this and having it committed to silicon
1 reply 0 retweets 0 likes
HT has 2+ execution contexts sharing a core (thus execution units, cache, just not register file & insn stream).
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