When people slam CPU manufacturers for Spectre, remember: Customers demanded speed doubling on legacy code, CPU vendors bent over backwards to accomodate programmers that did not want to learn parallelism.
Not unless you can avoid visibility across HT. You need a few hidden speculative-only cache lines per hw thread I suspect.
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But isn’t speculation bound to a core already? Oh what a horror to manage... I feel sorry for those engineers designing this and having it committed to silicon

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HT has 2+ execution contexts sharing a core (thus execution units, cache, just not register file & insn stream).
End of conversation
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