When people slam CPU manufacturers for Spectre, remember: Customers demanded speed doubling on legacy code, CPU vendors bent over backwards to accomodate programmers that did not want to learn parallelism.
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You said minimal performance impact. That won't be true. Hiding latency of cache miss by speculating on addresses crucial
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Tagging cache units with branch IDs and flush as branches become invalid?
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Flushing is pointless because the speculative load will invalidate the attackers cache line anyway, letting her know which line was loaded. We need a hidden cache that can somehow be made 'visible' when a speculated branch is taken. ARM spec allows hidden cache levels for e.g.
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I think it's also possible to speculatively fetch to visible cache as long as the address to fetch is a retired result, not speculative, but not 100% sure.
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It's definitely better than completely giving up on speculation, although I believe that was a necessary first step. The approach of putting in speculation barriers seems kinda naive though given the amount of understanding the average dev has even of memory barriers.
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Absolutely. Any approach that requires work by the programmer or compiler is fundamentally bogus.
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If compiler can do it, why is it bogus? We require compilers to allocate registers.
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Because that's a fundamental change to the ISA tgat renders existing software unsupported. A new ISA could require it, of course, but that seems dangerous & error-prone.
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