Wow some actual technical information on the spectre mitigation uc updates.https://twitter.com/johnregehr/status/955620344932442112 …
-
Show this thread
-
Any idea if they have a register to just turn off branch prediction yet?
1 reply 0 retweets 0 likesShow this thread -
Replying to @RichFelker
They do. Google's ret trampoline white paper talks about them "disabling branch prediction" for tests. So I think intel is just keeping us in the dark.
3 replies 0 retweets 0 likes -
Replying to @valarauca1 @RichFelker
1) retpoline is a substitute for indirect branches 2) retpoline is a construct that can be used on a case-by-case basis, it does not change the behavior of existing indirect branches 3) the actual instruction to do exactly what Rich asks is named and described in the linked post
1 reply 0 retweets 0 likes -
Replying to @volatile_void @valarauca1
One-off flush is not a disable. It does nothing to make running existing binaries safe.
1 reply 0 retweets 0 likes -
Replying to @RichFelker @valarauca1
Yes I realized that you just wanted an instruction to run once, not once per context switch. You’re better off switching to an in-order arch for that. I understand Atom still is in-order. I have a pentium from 1996 that I can give you, too.
2 replies 0 retweets 0 likes -
Replying to @volatile_void @valarauca1
Historically TR12 MSR bit 0 was NBP (no branch prediction) but I can't find if it still exists.
1 reply 0 retweets 1 like -
Replying to @RichFelker @valarauca1
Didn't it just disable dynamic branch prediction? Spectre-like vulnerabilities still exist with static prediction (you actually save the attacker the bother of poisoning the branch prediction first).
1 reply 0 retweets 0 likes
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.